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E-grāmata: Advanced Integrated Communication Microsystems

(Georgia Institute of Technology), (Georgia Institute of Technology), (University of California, Davis), (Georgia Institute of Technology)
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Learn the fundamentals of integrated communication microsystems Advanced communication microsystemsthe latest technology to emerge in the semiconductor sector after microprocessorsrequire integration of diverse signal processing blocks in a power-efficient and cost-effective manner. Typically, these systems include data acquisition, data processing, telemetry, and power management. The overall development is a synergy among system, circuit, and component-level designs with a strong emphasis on integration.

This book is targeted at students, researchers, and industry practitioners in the semiconductor area who require a thorough understanding of integrated communication microsystems from a developer's perspective. The book thoroughly and carefully explores:





Fundamental requirements of communication microsystems



System design and considerations for wired and wireless communication microsystems



Advanced block-level design techniques for communication microsystems



Integration of communication systems in a hybrid environment



Packaging considerations



Power and form factor trade-offs in building integrated microsystems





Advanced Integrated Communication Microsystems is an ideal textbook for advanced undergraduate and graduate courses. It also serves as a valuable reference for researchers and practitioners in circuit design for telecommunications and related fields.
Preface xv
Acknowledgments xix
1 Fundamental Concepts and Background 1
Introduction
1
1.1 Communication Systems
1
1.2 History and Overview of Wireless Communication Systems
3
1.3 History and Overview of Wired Communication Systems
4
1.4 Communication System Fundamentals
5
1.4.1 Channel Capacity
5
1.4.2 Bandwidth and Power Tradeoff
6
1.4.3 SNR as a Metric
7
1.4.4 Operating Frequency
8
1.4.5 The Cellular Concept
9
1.4.6 Digital Communications
10
1.4.7 Power Constraint
11
1.4.8 Symbol Constellation
12
1.4.9 Quadrature Basis and Sideband Combination
12
1.4.10 Negative Frequency
13
1.5 Electromagnetics
14
1.5.1 Maxwell's Equations
14
1.5.2 Application to Circuit Design
14
1.5.3 Signal Propagation in Wireless Medium
15
1.6 Analysis of Circuits and Systems
16
1.6.1 Laplace Transformation
16
1.6.2 Fourier Series
16
1.6.3 Fourier Transform
18
1.6.4 Time and Frequency Domain Duality
18
1.6.5 Z Transform
20
1.6.6 Circuit Dynamics
21
1.6.7 Frequency Domain and Time Domain Simulators
21
1.6.8 Matrix Representation of Circuits
21
1.6.8.1 S Parameters
22
1.6.8.2 Smith Chart
23
1.6.8.3 Practical Applications of S Parameters
24
1.7 Broadband, Wideband, and Narrowband Systems
26
1.7.1 LC Tank as a Narrowband Element
26
1.7.2 LC Tank at Resonance
27
1.7.3 Q Factor, Power, and Area Metrics
28
1.7.4 Silicon-Specific Considerations
28
1.7.5 Time Domain Behavior
29
1.7.6 Series/Parallel Resonance
29
1.8 Semiconductor Technology and Devices
30
1.8.1 Silicon-Based Processes
31
1.8.2 Unity Current and Power Gain
31
1.8.3 Noise
33
1.8.4 Bipolar vs. MOS
34
1.8.5 Device Characteristics
35
1.8.5.1 DC Characteristics
35
1.8.5.2 Output Impedance
35
1.8.5.3 Capacitive Elements
35
1.8.5.4 Device Noise
36
1.8.5.5 Breakdown Voltage
39
1.8.5.6 Technology Scaling
40
1.8.6 Passive Components
41
1.8.6.1 Resistors
41
1.8.6.2 Capacitors
42
1.8.6.3 Inductors
43
1.8.6.4 Transformers
50
1.8.7 Evaluation Testbenches
51
1.9 Key Circuit Topologies
55
1.9.1 Differential Circuits
55
1.9.2 Translinear Circuits
58
1.9.3 Feedback Circuits
59
1.9.3.1 Feedback in OP-AMPs
59
1.9.3.2 Virtual Ground
59
1.9.3.3 Miller's Theorem
60
1.9.4 Cascode Circuits
61
1.9.5 Common Source, Common Gate, and Common Drain Stages
62
1.9.6 Folded Cascode Topology
64
1.10 Gain/Linearity/Noise
65
1.10.1 Noise and Intermodulation Tradeoff
65
1.10.2 Narrowband and Wideband Systems
66
Conclusion
66
References
66
2 Wireless Communication System Architectures 69
Introduction
69
2.1 Fundamental Considerations
70
2.1.1 Center Frequency, Modulation, and Process Technology
70
2.1.2 Frequency Planning
71
2.1.3 Blockers
72
2.1.4 Spurs and Desensing
74
2.1.5 Transmitter Leakage
74
2.1.6 LO leakage and Interference
74
2.1.7 Image
76
2.1.8 Half-IF Interference
76
2.2 Link Budget Analysis
77
2.2.1 Linearity
77
2.2.2 Noise
80
2.2.2.1 Thermal Noise
80
2.2.2.2 Transmitter Noise
80
2.2.2.3 Phase Noise
81
2.2.3 Signal-to-Noise Ratio
82
2.2.4 Receiver Gain
82
2.3 Propagation Effects
83
2.3.1 Path Loss
83
2.3.2 Multipath and Fading
85
2.3.3 Equalization
86
2.3.4 Diversity
86
2.3.5 Coding
87
2.4 Interface Planning
87
2.5 Superheterodyne Architecture
87
2.5.1 Frequency Domain Representation
88
2.5.2 Phase Shift and Image Rejection
89
2.5.3 Transmitter and Receiver
90
2.5.4 Imbalance and Harmonics
90
2.6 Low IF Architecture
91
2.7 Direct Conversion Architecture
92
2.7.1 Advantages
93
2.7.2 Modulation
93
2.7.3 Architecture and Frequency Planning
93
2.7.4 Challenges in the Direct Conversion Receiver
94
2.7.4.1 Finite IIP2, IIP3
94
2.7.4.2 DC Offset
97
2.7.4.3 LO Leakage
99
2.7.4.4 I/Q Imbalance
100
2.7.4.5 LO Pulling
101
2.7.4.6 TX-RX Crosstalk
101
2.7.4.7 Flicker Noise
102
2.8 Two-Stage Direct Conversion
102
2.9 Current-Mode Architecture
103
2.10 Subsampling Architecture
104
2.11 Multiband Direct Conversion Radio
105
2.12 Polar Modulator
106
2.13 Harmonic Reject Architecture
108
2.14 Practical Considerations for Transceiver Integration
109
2.14.1 Transmitter Considerations
109
2.14.2 Receiver Considerations
110
Conclusion
111
References
111
3 System Architecture for High-Speed Wired Communications 113
Introduction
113
3.1 Bandlimited Channel
118
3.1.1 Fiber Optical Link
118
3.1.2 Dispersion in Fibers
120
3.1.3 Backplane Multi-Gb/s Data Interface
123
3.1.4 Backplane Channel Loss
124
3.1.4.1 DC Loss
125
3.1.4.2 The Skin Effect
126
3.1.4.3 Dielectric Loss
126
3.1.4.4 Impacts of Channel Loss on the Signal Integrity
127
3.2 Equalizer System Study
129
3.2.1 Equalization Overview
129
3.2.2 Historical Background
131
3.2.3 Equalizer Topology Study
133
3.2.3.1 Liner Equalizer
134
3.2.3.2 Nonlinear Equalizers
136
3.2.3.3 Cable Equalizer (Bode Equalizer)
137
3.2.3.4 Transmitter- and Receiver-Side Equalizer
137
3.2.4 Equalizer System Simulation
139
Conclusion
143
References
143
4 Mixed Building Blocks of Signal Communication Systems 144
Introduction
144
4.1 Inverters
145
4.1.1 Key Design Parameters
145
4.1.2 Key Electrical Equations
146
4.1.3 Current Reuse Amplifier
147
4.1.4 Cascade and Fan-Out
148
4.2 Static D Flip-Flop
148
4.3 Bias Circuits
151
4.3.1 Current Sources and Sinks
151
4.3.2 Voltage References
153
4.4 Transconductor Cores
154
4.5 Load Networks
157
4.5.1 Passive Load
157
4.5.2 Active Load
158
4.6 A Versatile Analog Signal Processing Core
159
4.7 Low Noise Amplifier
162
4.7.1 Single-Ended Interfaces
163
4.7.2 Design Steps
163
4.7.3 Gain Expansion
165
4.7.4 Layout Considerations
165
4.7.5 Inductorless LNAs
166
4.7.6 Gain Variation
166
4.8 Power Amplifiers
168
4.8.1 Performance Metrics
168
4.8.1.1 Linearity and its Measures
168
4.8.1.2 Efficiency and its Measures
169
4.8.2 Classes of Amplifiers
170
4.8.2.1 Class A
170
4.8.2.2 Class B
171
4.8.2.3 Class C
171
4.8.2.4 Class D
171
4.8.2.5 Class E
172
4.8.2.6 Class F
172
4.8.3 Practical Considerations
172
4.8.4 PA Architectures
172
4.8.4.1 Device Geometry
172
4.8.4.2 Cascades of PAs
172
4.8.4.3 Bypassing/Switching Stages
173
4.8.4.4 Envelope Elimination and Restoration
173
4.8.4.5 Outphasing
174
4.8.4.6 Doherty Amplifier
174
4.8.5 Feedback and Feedforward
174
4.8.5.1 Envelope Feedback
174
4.8.5.2 Polar Feedback Technique
175
4.8.5.3 Cartesian Feedback Technique
175
4.8.5.4 Feedforward Technique
176
4.8.6 Predistortion Techniques
177
4.9 Balun
178
4.10 Signal Generation Path
179
4.10.1 Oscillator Circuits
179
4.10.1.1 LC Oscillators
180
4.10.1.2 Ring Oscillators
187
4.10.2 Quadrature Generation Networks
188
4.10.2.1 D Latch-Based Divider
188
4.10.2.2 Polyphase Quadrature Generators
191
4.10.3 Passive Hybrid Networks
194
4.10.4 Regenerative Frequency Dividers
194
4.10.5 Phase Locked Loop
195
4.10.5.1 Impact of VCO Frequency Resolution
195
4.10.5.2 Complicated Divide Ratios
196
4.10.5.3 PLL Loop and Dynamics
197
4.11 Mixers
201
4.11.1 Basic Functionality
201
4.11.2 Architectures
202
4.11.3 Conversion Gain/Loss
203
4.11.4 Noise
204
4.11.5 Port Isolation
205
4.11.6 Receive and Transmit Mixers
205
4.11.7 Impedances
206
4.12 Baseband Filters
207
4.12.1 Classification of Integrated Filters
207
4.12.2 Biquadratic Stages
208
4.12.3 Switched Capacitor Filters
209
4.12.4 Gm-C Filters
211
4.12.5 OP-Amp-RC Filters
213
4.12.5.1 Voltage-Limiting Behavior
215
4.12.5.2 Current-Limiting Behavior
217
4.12.5.3 Phase Rotation
217
4.12.5.4 Architectural Considerations
218
4.12.5.5 Multiorder Continuous-Time Active Filters
218
4.12.5.6 Common-Mode Levels
219
4.12.5.7 OP-Amp Design
219
4.12.5.8 R–C Switching Banks
221
4.12.5.9 Stability Analysis of Filters
222
4.12.6 Calibration of On-Chip Filters
224
4.12.7 Passive Filter Configuration
226
4.13 Signal Strength Indicator (SSI)
226
4.14 ADC/DAC
227
4.15 Latch
230
Conclusion
231
References
231
5 Examples of Integrated Communication Microsystems 235
Introduction
235
5.1 Direct Conversion Receiver Front End
235
5.1.1 Circuit Design
236
5.1.1.1 LNA Design
237
5.1.1.2 Mixer Design
238
5.1.1.3 Signal Generation Path
241
5.1.2 The Integration: Interfaces and Layout
242
5.1.3 Compensation and Corrections
243
5.2 Debugging: A Practical Scenario
244
5.3 High-Speed Wired Communication Example
245
5.3.1 Bandlimited Channel
245
5.3.2 Design Example
247
5.3.2.1 Feed-Forward Equalizer (FFE)
247
5.3.2.2 FFE with the Passive Delay Line Approach
248
5.3.2.3 Reconfigurable Equalizer System Overview
250
5.3.2.4 FFE with Active Delay Line
252
5.3.2.5 CMOS Building Blocks for Reconfigurable Equalizer
254
Conclusion
258
References
258
6 Low-Voltage, Low-Power, and Low-Area Designs 260
Introduction
260
6.1 Power Consumption Considerations
261
6.1.1 Active Inductors
261
6.1.2 Adding Transfer Function Zero
263
6.1.3 Driving Point Impedance
263
6.1.4 Stacking Functional Blocks
265
6.2 Device Technology and Scaling
266
6.2.1 Digital and Analog Circuits
266
6.2.2 Supply Voltage, Speed, and Breakdown
266
6.2.3 Circuit Impacts of Increased fT
267
6.2.4 MOSFETs in Weak Inversion
267
6.2.5 Millimeter-Wave Applications
268
6.2.6 Practical Considerations
268
6.3 Low-Voltage Design Techniques
269
6.3.1 Separate DC Paths per Circuit Functionality
269
6.3.2 Transformer Coupled Feedback
270
6.3.3 Positive Feedback
271
6.3.4 Current-Mode Interface
272
6.3.5 Circuits Based on Weak Inversion
273
6.3.6 Voltage Boosting
273
6.3.7 Bulk-Driven Circuits
274
6.3.8 Flipped Voltage Follower
276
6.4 Injection-Locked Techniques
277
6.5 Subharmonic Architectures
279
6.5.1 Formalism
279
6.5.2 System Considerations
280
6.5.3 Antiparallel Diode Pair
281
6.5.4 Active Subharmonic Mixers
284
6.5.5 Subharmonic Architecture Building Blocks
286
6.6 Super-Regenerative Architectures
286
6.6.1 Formalism
287
6.6.2 Architecture and Circuit Illustration
289
6.7 Hearing Aid Applications
290
6.7.1 Architecture Based on Digital/Mixed-Signal Circuits
290
6.7.2 Architecture Based on Subthreshold Current-Mode Circuits
292
6.8 Radio Frequency Identification Tags
297
6.8.1 System Considerations
297
6.8.2 System Architecture
297
6.8.3 Rectifier, Limiter, and Regulator
298
6.8.4 Antenna Design
301
6.9 Ultra-Low-Power Radios
302
Conclusion
303
References
304
7 Packaging for Integrated Communication Microsystems 309
Introduction
309
7.1 Background
311
7.1.1 Trends from 1970 to 1995
311
7.1.2 Trends from 1995 to Today
313
7.1.3 Before 2006
314
7.1.4 After 2006
314
7.2 Elements of a Package
315
7.2.1 Power/GND Planes
315
7.2.2 Package Materials
317
7.3 Current Chip Packaging Technologies
317
7.3.1 Ball Grid Arrays (BGAs)
317
7.3.2 Flip-Chip Technology (FCT)
319
7.3.3 Flip-Chip vs. Wire Bond
319
7.3.4 Choice of Transmission Line
320
7.3.5 Thermal Issues
320
7.3.6 Chip Scale Packaging (CSP)
321
7.4 Driving Forces for RF Packaging Technology
322
7.5 MCM Definitions and Classifications
323
7.6 RF—SOP Modules
325
7.7 Package Modeling and Optimization
329
7.8 Future Packaging Trends
333
7.9 Chip-Package Codesign
334
7.10 Package Models and Transmission Lines
335
7.10.1 Frequency of Operations
335
7.10.2 Bends and Discontinuities
336
7.10.3 Differential Signaling
337
7.11 Calculations for Package Elements
339
7.11.1 Inductance
339
7.11.2 Capacitance
340
7.11.3 Image Theory
341
7.12 Crosstalk
342
7.13 Grounding
343
7.14 Practical Issues in Packaging
344
7.14.1 Ground Modeling
344
7.14.2 Isolation
345
7.15 Chip-Package Codesign Examples
346
7.15.1 Tuned Amplifier with Off-Chip Inductor
346
7.15.2 LNA and Oscillator
347
7.15.3 Magnetic Crosstalk
348
7.16 Wafer Scale Package
349
7.17 Filters Using Bondwire
349
7.18 Packaging Limitation
350
Conclusion
351
References
351
8 Advanced SOP Components and Signal Processing 355
Introduction
355
8.1 History of Compact Design
358
8.2 Previous Techniques in Performance Enhancement
361
8.3 Design Complexities
363
8.4 Modeling Complexities
363
8.5 Compact Stacked Patch Antennas Using LTCC Multilayer Technology
365
8.6 Suppression of Surface Waves and Radiation Pattern Improvement Using SHS Technology
378
8.7 Radiation-Pattern Improvement Using a Compact Soft-Surface Structure
382
8.8 A Package-Level-Integrated Antenna Based on LTCC Technology
395
Conclusion
401
References
401
9 Simulation and Characterization of Integrated Microsystems 404
Introduction
404
9.1 Computer-Aided Analysis of Wireless Systems
404
9.1.1 Operating Point Analysis
405
9.1.2 Impedance Matching
407
9.1.3 Tuning at Resonance
407
9.1.4 Transient Analysis
408
9.1.5 Noise Analysis
409
9.1.6 Linearity Analysis
410
9.1.7 Parasitic Elements
413
9.1.8 Process Variation
413
9.2 Measurement Equipments and their Operation
413
9.2.1 DC/Operating Point
413
9.2.2 C–V Measurement
414
9.2.3 Vector Network Analyzer and S-Parameter Measurements
415
9.2.4 Spectrum Analyzer (SA)
416
9.3 Network Analyzer Calibration
418
9.3.1 Overview of Network Analyzer Calibration
418
9.3.2 Types of Calibration
420
9.3.3 SOLT Calibration
420
9.3.4. TRL Calibration
424
9.4 Wafer Probing Measurement
429
9.4.1 Calibration Quantification of Random Errors
429
9.4.2 On-Wafer Measurement at the W-Band (75-110 GHz)
430
9.4.2.1 Measurement Setup
430
9.4.2.2 On-Wafer Calibration at the W-Band (75-110 GHz)
432
9.4.2.3 Repeatability Study
433
9.4.2.4 Cross-Talk between Two CPW Microprobes
434
9.4.3 On-Wafer Microstrip Characterization Techniques
435
9.4.3.1 CPW/MS Calibration Kit
437
9.4.4 On-Wafer Package Characterization Technique
440
9.4.4.1 On-Wafer Package Adapters
440
9.4.4.2 On-Wafer Package Adapter Calibration Kit
440
9.4.4.3 Experiment and Packaging Modeling
443
9.4.4.4 Application of Package Model in Active Devices
445
9.5 Characterization of Integrated Radios
448
9.6 In the Lab
451
9.6.1 Operating Point
451
9.6.2 Functionality Test
451
9.6.3 Impedance Matching
451
9.6.4 Conversion Gain
453
9.6.5 Linearity
453
9.6.6 Nonlinear Noise Figure
454
9.6.7 I/Q Imbalance
455
9.6.8 DC Offset
456
Conclusion
457
References
458
Appendix A Compendium of the TRL Calibration Algorithm 459
Appendix A
462
Index 469
Joy Laskar, PhD, holds the Schlumberger Chair in Microelectronics in the School of Electrical and Computer Engineering at Georgia Tech. He is also founder and Director of the Georgia Electronic Design Center, where he heads a research group that focuses on the integration of high-frequency mixed-signal electronics for next-generation wireless and wire line systems.

Sudipto Chakraborty, PhD, is a research staff member at Texas Instruments, where he is involved in architecting and designing advanced system-on-chip mixed signal systems using silicon-based technologies. He has authored or coauthored several technical articles, journals, and books, and has served on the technical program committee for various IEEE conferences and journals.

Manos M. Tentzeris, PhD, is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He is also the Associate Director of the Georgia Electronic Design Center in the area of RFID/Sensors and heads the ATHENA group, which focuses on 3D integration and packaging, multiband/ultrawideband antennas and antenna arrays, wearable/flexible inkjet-printed electronics, CNT/graphene, and integrable power scavenging.

Franklin Bien, PhD, is an Assistant Professor at Ulsan National Institute of Science and Technology (UNIST), Korea, home for Hyundai/Kia Motor Company. He cofounded and leads the UNIST Electronic Design Center (UEDC) focusing on analog/mixed-signal and RF ICs for wireless communications and ubiquitous connectivity for automotive information technology applications.

Anh-Vu Pham, PhD, is a Professor at the University of California, Davis, where he leads the Microwave Microsystems Lab. He has published extensively and received the National Science Foundation CAREER Award in 2001 and the 2008 Outstanding Young Engineer Award from the IEEE Microwave Theory and Techniques Society. He cofounded RF Solutions and PlanarMag, Inc., and has been an active consultant for industry.
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