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Analysis and Design of Analog Integrated Circuits, International Student Version 5th edition [Mīkstie vāki]

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(University of California, Davis), , (University of California, Berkeley), (University of California, Berkeley)
  • Formāts: Paperback / softback, 896 pages, height x width x depth: 254x178x38 mm, weight: 1828 g
  • Izdošanas datums: 08-May-2009
  • Izdevniecība: John Wiley & Sons Inc
  • ISBN-10: 0470398779
  • ISBN-13: 9780470398777
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Analysis and Design of Analog Integrated Circuits, International Student Version 5th editionPalielināt
  • Formāts: Paperback / softback, 896 pages, height x width x depth: 254x178x38 mm, weight: 1828 g
  • Izdošanas datums: 08-May-2009
  • Izdevniecība: John Wiley & Sons Inc
  • ISBN-10: 0470398779
  • ISBN-13: 9780470398777
Citas grāmatas par šo tēmu:
Permanent link: https://www.kriso.lv/db/9780470398777.html
This is the only comprehensive book in the market for engineers that covers the design of CMOS and bipolar analog integrated circuits. The fifth edition retains its completeness and updates the coverage of bipolar and CMOS circuits.
A thorough analysis of a new low-voltage bipolar operational amplifier has been added to Chapters 6, 7, 9, and 11.
Chapter 12 has been updated to include a fully differential folded cascode operational amplifier example. With its streamlined and up-to-date coverage, more engineers will turn to this resource to explore key concepts in the field.

Recenzijas

"Intended both for students and as a reference for working engineers, the fifth edition of this popular engineering textbook is updated to include discussions of newly available integrated circuits as well as general advances in the field. Drawn from material taught to high level seniors and graduate students at the University of California's Berkeley and Davis engineering departments, the work covers such topics as the physics of bipolar and MOS transistors, the technology of integrated circuit (IC) fabrication and the design and uses of operational amplifiers as well as many advanced topics in IC principles and design." (Reference and Research Book News, February 2011)

Chapter 1 Models for Integrated-Circuit Active Devices
1(77)
1.1 Introduction
1(1)
1.2 Depletion Region of a pn Junction
1(7)
1.2.1 Depletion-Region Capacitance
5(1)
1.2.2 Junction Breakdown
6(2)
1.3 Large-Signal Behavior of Bipolar Transistors
8(17)
1.3.1 Large-Signal Models in the Forward-Active Region
8(6)
1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region
14(2)
1.3.3 Saturation and Inverse-Active Regions
16(4)
1.3.4 Transistor Breakdown Voltages
20(3)
1.3.5 Dependence of Transistor Current Gain fiF on Operating Conditions
23(2)
1.4 Small-Signal Models of Bipolar Transistors
25(13)
1.4.1 Transconductance
26(1)
1.4.2 Base-Charging Capacitance
27(1)
1.4.3 Input Resistance
28(1)
1.4.4 Output Resistance
29(1)
1.4.5 Basic Small-Signal Model of the Bipolar Transistor
30(1)
1.4.6 Collector-Base Resistance
30(1)
1.4.7 Parasitic Elements in the Small-Signal Model
31(3)
1.4.8 Specification of Transistor Frequency Response
34(4)
1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors
38(11)
1.5.1 Transfer Characteristics of MOS Devices
38(7)
1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors
45(2)
1.5.3 Decomposition of Gate-Source Voltage
47(1)
1.5.4 Threshold Temperature Dependence
47(1)
1.5.5 MOS Device Voltage Limitations
48(1)
1.6 Small-Signal Models of MOS Transistors
49(10)
1.6.1 Transconductance
50(1)
1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance
51(1)
1.6.3 Input Resistance
52(1)
1.6.4 Output Resistance
52(1)
1.6.5 Basic Small-Signal Model of the MOS Transistor
52(1)
1.6.6 Body Transconductance
53(1)
1.6.7 Parasitic Elements in the Small-Signal Model
54(1)
1.6.8 MOS Transistor Frequency Response
55(4)
1.7 Short-Channel Effects in MOS Transistors
59(6)
1.7.1 Velocity Saturation from the Horizontal Field
59(4)
1.7.2 Transconductance and Transition Frequency
63(2)
1.7.3 Mobility Degradation from the Vertical Field
65(1)
1.8 Weak Inversion in MOS Transistors
65(6)
1.8.1 Drain Current in Weak Inversion
66(3)
1.8.2 Transconductance and Transition Frequency in Weak Inversion
69(2)
1.9 Substrate Current Flow in MOS Transistors
71(7)
A.1.1 Summary of Active-Device Parameters
73(5)
Chapter 2 Bipolar, MOS, and BiCMOS Integrated-Circuit Technology
78(91)
2.1 Introduction
78(1)
2.2 Basic Processes in Integrated-Circuit Fabrication
79(9)
2.2.1 Electrical Resistivity of Silicon
79(1)
2.2.2 Solid-State Diffusion
80(2)
2.2.3 Electrical Properties of Diffused Layers
82(2)
2.2.4 Photolithography
84(2)
2.2.5 Epitaxial Growth
86(1)
2.2.6 Ion Implantation
87(1)
2.2.7 Local Oxidation
87(1)
2.2.8 Polysilicon Deposition
87(1)
2.3 High-Voltage Bipolar Integrated-Circuit Fabrication
88(4)
2.4 Advanced Bipolar Integrated-Circuit Fabrication
92(3)
2.5 Active Devices in Bipolar Analog Integrated Circuits
95(20)
2.5.1 Integrated-Circuit npn Transistors
96(11)
2.5.2 Integrated-Circuit pnp Transistors
107(8)
2.6 Passive Components in Bipolar Integrated Circuits
115(8)
2.6.1 Diffused Resistors
115(4)
2.6.2 Epitaxial and Epitaxial Pinch Resistors
119(1)
2.6.3 Integrated-Circuit Capacitors
120(1)
2.6.4 Zener Diodes
121(1)
2.6.5 Junction Diodes
122(1)
2.7 Modifications to the Basic Bipolar Process
123(4)
2.7.1 Dielectric Isolation
123(1)
2.7.2 Compatible Processing for High-Performance Active Devices
124(3)
2.7.3 High-Performance Passive Components
127(1)
2.8 MOS Integrated-Circuit Fabrication
127(4)
2.9 Active Devices in MOS Integrated Circuits
131(15)
2.9.1 n-Channel Transistors
131(13)
2.9.2 p-Channel Transistors
144(1)
2.9.3 Depletion Devices
144(1)
2.9.4 Bipolar Transistors
145(1)
2.10 Passive Components in MOS Technology
146(6)
2.10.1 Resistors
146(2)
2.10.2 Capacitors in MOS Technology
148(3)
2.10.3 Latchup in CMOS Technology
151(1)
2.11 BiCMOS Technology
152(1)
2.12 Heterojunction Bipolar Transistors
153(3)
2.13 Interconnect Delay
156(1)
2.14 Economics of Integrated-Circuit Fabrication
156(13)
2.14.1 Yield Considerations in Integrated-Circuit Fabrication
157(2)
2.14.2 Cost Considerations in Integrated-Circuit Fabrication
159(3)
A.2.1 SPICE Model-Parameter Files
162(7)
Chapter 3 Single-Transistor and Multiple-Transistor Amplifiers
169(82)
3.1 Device Model Selection for Approximate Analysis of Analog Circuits
170(1)
3.2 Two-Port Modeling of Amplifiers
171(2)
3.3 Basic Single-Transistor Amplifier Stages
173(28)
3.3.1 Common-Emitter Configuration
174(4)
3.3.2 Common-Source Configuration
178(4)
3.3.3 Common-Base Configuration
182(3)
3.3.4 Common-Gate Configuration
185(2)
3.3.5 Common-Base and Common-Gate Configurations with Finite ro
187(1)
3.3.5.1 Common-Base and Common-Gate Input Resistance
187(2)
3.3.5.2 Common-Base and Common-Gate Output Resistance
189(2)
3.3.6 Common-Collector Configuration (Emitter Follower)
191(3)
3.3.7 Common-Drain Configuration (Source Follower)
194(2)
3.3.8 Common-Emitter Amplifier with Emitter Degeneration
196(3)
3.3.9 Common-Source Amplifier with Source Degeneration
199(2)
3.4 Multiple-Transistor Amplifier Stages
201(13)
3.4.1 The CC-CE, CC-CC, and Darlington Configurations
201(4)
3.4.2 The Cascode Configuration
205(1)
3.4.2.1 The Bipolar Cascode
205(2)
3.4.2.2 The MOS Cascode
207(3)
3.4.3 The Active Cascode
210(2)
3.4.4 The Super Source Follower
212(2)
3.5 Differential Pairs
214(37)
3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair
214(2)
3.5.2 The dc Transfer Characteristic with Emitter Degeneration
216(1)
3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair
217(3)
3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers
220(3)
3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers
223(6)
3.5.6 Device Mismatch Effects in Differential Amplifiers
229(1)
3.5.6.1 Input Offset Voltage and Current
230(1)
3.5.6.2 Input Offset Voltage of the Emitter-Coupled Pair
230(1)
3.5.6.3 Offset Voltage of the Emitter-Coupled Pair: Approximate Analysis
231(2)
3.5.6.4 Offset Voltage Drift in the Emitter-Coupled Pair
233(1)
3.5.6.5 Input Offset Current of the Emitter-Coupled Pair
233(1)
3.5.6.6 Input Offset Voltage of the Source-Coupled Pair
234(1)
3.5.6.7 Offset Voltage of the Source-Coupled Pair: Approximate Analysis
235(1)
3.5.6.8 Offset Voltage Drift in the Source-Coupled Pair
236(1)
3.5.6.9 Small-Signal Characteristics of Unbalanced Differential Amplifiers
237(7)
A.3.1 Elementary Statistics and the Gaussian Distribution
244(7)
Chapter 4 Current Mirrors, Active Loads, and References
251(90)
4.1 Introduction
251(1)
4.2 Current Mirrors
251(25)
4.2.1 General Properties
251(2)
4.2.2 Simple Current Mirror
253(1)
4.2.2.1 Bipolar
253(2)
4.2.2.2 MOS
255(3)
4.2.3 Simple Current Mirror with Beta Helper
258(1)
4.2.3.1 Bipolar
258(2)
4.2.3.2 MOS
260(1)
4.2.4 Simple Current Mirror with Degeneration
260(1)
4.2.4.1 Bipolar
260(1)
4.2.4.2 MOS
261(1)
4.2.5 Cascode Current Mirror
261(1)
4.2.5.1 Bipolar
261(3)
4.2.5.2 MOS
264(8)
4.2.6 Wilson Current Mirror
272(1)
4.2.6.1 Bipolar
272(3)
4.2.6.2 MOS
275(1)
4.3 Active Loads
276(21)
4.3.1 Motivation
276(1)
4.3.2 Common-Emitter-Common-Source Amplifier with Complementary Load
277(3)
4.3.3 Common-Emitter-Common-Source Amplifier with Depletion Load
280(2)
4.3.4 Common-Emitter-Common-Source Amplifier with Diode-Connected Load
282(3)
4.3.5 Differential Pair with Current-Mirror Load
285(1)
4.3.5.1 Large-Signal Analysis
285(1)
4.3.5.2 Small-Signal Analysis
286(5)
4.3.5.3 Common-Mode Rejection Ratio
291(6)
4.4 Voltage and Current References
297(44)
4.4.1 Low-Current Biasing
297(1)
4.4.1.1 Bipolar Widlar Current Source
297(3)
4.4.1.2 MOS Widlar Current Source
300(1)
4.4.1.3 Bipolar Peaking Current Source
301(1)
4.4.1.4 MOS Peaking Current Source
302(1)
4.4.2 Supply-Insensitive Biasing
303(1)
4.4.2.1 Widlar Current Sources
304(1)
4.4.2.2 Current Sources Using Other Voltage Standards
305(2)
4.4.2.3 Self-Biasing
307(8)
4.4.3 Temperature-Insensitive Biasing
315(1)
4.4.3.1 Band-Gap-Referenced Bias Circuits in Bipolar Technology
315(6)
4.4.3.2 Band-Gap-Referenced Bias Circuits in CMOS Technology
321(4)
A.4.1 Matching Considerations in Current Mirrors
325(1)
A.4.1.1 Bipolar
325(3)
A.4.1.2 MOS
328(2)
A.4.2 Input Offset Voltage of Differential Pair with Active Load
330(1)
A.4.2.1 Bipolar
330(2)
A.4.2.2 MOS
332(9)
Chapter 5 Output Stages
341(59)
5.1 Introduction
341(1)
5.2 The Emitter Follower as an Output Stage
341(12)
5.2.1 Transfer Characteristics of the Emitter-Follower
341(3)
5.2.2 Power Output and Efficiency
344(7)
5.2.3 Emitter-Follower Drive Requirements
351(1)
5.2.4 Small-Signal Properties of the Emitter Follower
352(1)
5.3 The Source Follower as an Output Stage
353(6)
5.3.1 Transfer Characteristics of the Source Follower
353(2)
5.3.2 Distortion in the Source Follower
355(4)
5.4 Class B Push-Pull Output Stage
359(20)
5.4.1 Transfer Characteristic of the Class B Stage
360(2)
5.4.2 Power Output and Efficiency of the Class B Stage
362(4)
5.4.3 Practical Realizations of Class B Complementary Output Stages
366(7)
5.4.4 A\\-npn Class B Output Stage
373(3)
5.4.5 Quasi-Complementary Output Stages
376(1)
5.4.6 Overload Protection
377(2)
5.5 CMOS Class AB Output Stages
379(21)
5.5.1 Common-Drain Configuration
380(1)
5.5.2 Common-Source Configuration with Error Amplifiers
381(7)
5.5.3 Alternative Configurations
388(1)
5.5.3.1 Combined Common-Drain Common-Source Configuration
388(2)
5.5.3.2 Combined Common-Drain Common-Source Configuration with High Swing
390(1)
5.5.3.3 Parallel Common-Source Configuration
390(10)
Chapter 6 Operational Amplifiers with Single-Ended Outputs
400(90)
5.1 Applications of Operational Amplifiers
401(14)
6.1.1 Basic Feedback Concepts
401(1)
6.1.2 Inverting Amplifier
402(2)
6.1.3 Noninverting Amplifier
404(1)
6.1.4 Differential Amplifier
404(1)
6.1.5 Nonlinear Analog Operations
405(1)
6.1.6 Integrator, Differentiator
406(1)
6.1.7 Internal Amplifiers
407(1)
6.1.7.1 Switched-Capacitor Amplifier
407(5)
6.1.7.2 Switched-Capacitor Integrator
412(3)
6.2 Deviations from Ideality in Real Operational Amplifiers
415(6)
6.2.1 Input Bias Current
415(1)
6.2.2 Input Offset Current
416(1)
6.2.3 Input Offset Voltage
416(1)
6.2.4 Common-Mode Input Range
416(1)
6.2.5 Common-Mode Rejection Ratio (CMRR)
417(1)
6.2.6 Power-Supply Rejection Ratio (PSRR)
418(2)
6.2.7 Input Resistance
420(1)
6.2.8 Output Resistance
420(1)
6.2.9 Frequency Response
420(1)
6.2.10 Operational-Amplifier Equivalent Circuit
420(1)
6.3 Basic Two-Stage MOS Operational Amplifiers
421(17)
6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain
422(1)
6.3.2 Output Swing
423(1)
6.3.3 Input Offset Voltage
424(3)
6.3.4 Common-Mode Rejection Ratio
427(1)
6.3.5 Common-Mode Input Range
427(3)
6.3.6 Power-Supply Rejection Ratio (PSRR)
430(4)
6.3.7 Effect of Overdrive Voltages
434(1)
6.3.8 Layout Considerations
435(3)
6.4 Two-Stage MOS Operational Amplifiers with Cascodes
438(1)
6.5 MOS Telescopic-Cascode Operational Amplifiers
439(3)
6.6 MOS Folded-Cascode Operational Amplifiers
442(4)
6.7 MOS Active-Cascode Operational Amplifiers
446(2)
6.8 Bipolar Operational Amplifiers
448(42)
6.8.1 The dc Analysis of the NE5234 Operational Amplifier
452(15)
6.8.2 Transistors that Are Normally Off
467(2)
6.8.3 Small-Signal Analysis of the NE5234 Operational Amplifier
469(8)
6.8.4 Calculation of the Input Offset Voltage and Current of the NE5234
477(13)
Chapter 7 Frequency Response of Integrated Circuits
490(63)
7.1 Introduction
490(1)
7.2 Single-Stage Amplifiers
490(28)
7.2.1 Single-Stage Voltage Amplifiers and the Miller Effect
490(5)
7.2.1.1 The Bipolar Differential Amplifier: Differential-Mode Gain
495(4)
7.2.1.2 The MOS Differential Amplifier: Differential-Mode Gain
499(2)
7.2.2 Frequency Response of the Common-Mode Gain for a Differential Amplifier
501(2)
7.2.3 Frequency Response of Voltage Buffers
503(2)
7.2.3.1 Frequency Response of the Emitter Follower
505(6)
7.2.3.2 Frequency Response of the Source Follower
511(3)
7.2.4 Frequency Response of Current Buffers
514(2)
7.2.4.1 Common-Base Amplifier Frequency Response
516(1)
7.2.4.2 Common-Gate Amplifier Frequency Response
517(1)
7.3 Multistage Amplifier Frequency Response
518(21)
7.3.1 Dominant-Pole Approximation
518(1)
7.3.2 Zero-Value Time Constant Analysis
519(5)
7.3.3 Cascode Voltage-Amplifier Frequency Response
524(3)
7.3.4 Cascode Frequency Response
527(7)
7.3.5 Frequency Response of a Current Mirror Loading a Differential Pair
534(2)
7.3.6 Short-Circuit Time Constants
536(3)
7.4 Analysis of the Frequency Response of the NE5234 Op Amp
539(3)
7.4.1 High-Frequency Equivalent Circuit of the NE5234
539(1)
7.4.2 Calculation of the --3-dB Frequency oftheNE5234
540(2)
7.4.3 Nondominant Poles of the NE5234
542(1)
7.5 Relation Between Frequency Response and Time Response
542(11)
Chapter 8 Feedback
553(71)
8.1 Ideal Feedback Equation
553(2)
8.2 Gain Sensitivity
555(1)
8.3 Effect of Negative Feedback on Distortion
555(2)
8.4 Feedback Configurations
557(6)
8.4.1 Series-Shunt Feedback
557(3)
8.4.2 Shunt-Shunt Feedback
560(1)
8.4.3 Shunt-Series Feedback
561(1)
8.4.4 Series-Series Feedback
562(1)
8.5 Practical Configurations and the Effect of Loading
563(24)
8.5.1 Shunt-Shunt Feedback
563(6)
8.5.2 Series-Series Feedback
569(10)
8.5.3 Series-Shunt Feedback
579(4)
8.5.4 Shunt-Series Feedback
583(4)
8.5.5 Summary
587(1)
8.6 Single-Stage Feedback
587(6)
8.6.1 Local Series-Series Feedback
587(4)
8.6.2 Local Series-Shunt Feedback
591(2)
8.7 The Voltage Regulator as a Feedback Circuit
593(6)
8.8 Feedback Circuit Analysis Using Return Ratio
599(14)
8.8.1 Closed-Loop Gain Using Return Ratio
601(6)
8.8.2 Closed-Loop Impedance Formula Using Return Ratio
607(5)
8.8.3 Summary--Return-Ratio Analysis
612(1)
8.9 Modeling Input and Output Ports in Feedback Circuits
613(11)
Chapter 9 Frequency Response and Stability of Feedback Amplifiers
624(80)
9.1 Introduction
624(1)
9.2 Relation Between Gain and Bandwidth in Feedback Amplifiers
624(2)
9.3 Instability and the Nyquist Criterion
626(7)
9.4 Compensation
633(31)
9.4.1 Theory of Compensation
633(4)
9.4.2 Methods of Compensation
637(6)
9.4.3 Two-Stage MOS Amplifier Compensation
643(7)
9.4.4 Compensation of Single-Stage CMOS Op Amps
650(4)
9.4.5 Nested Miller Compensation
654(10)
9.5 Root-Locus Techniques
664(17)
9.5.1 Root Locus for a Three-Pole Transfer Function
665(2)
9.5.2 Rules for Root-Locus Construction
667(9)
9.5.3 Root Locus for Dominant-Pole Compensation
676(1)
9.5.4 Root Locus for Feedback-Zero Compensation
677(4)
9.6 Slew Rate
681(23)
9.6.1 Origin of Slew-Rate Limitations
681(4)
9.6.2 Methods of Improving Slew-Rate in Two-Stage Op Amps
685(2)
9.6.3 Improving Slew-Rate in Bipolar Op Amps
687(1)
9.6.4 Improving Slew-Rate in MOS Op Amps
688(4)
9.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance
692(1)
A.9.1 Analysis in Terms of Return-Ratio Parameters
693(1)
A.9.2 Roots of a Quadratic Equation
694(10)
Chapter 10 Nonlinear Analog Circuits
704(32)
10.1 Introduction
704(1)
10.2 Analog Multipliers Employing the Bipolar Transistor
704(12)
10.2.1 The Emitter-Coupled Pair as a Simple Multiplier
704(2)
10.2.2 The dc Analysis of the Gilbert Multiplier Cell
706(2)
10.2.3 The Gilbert Cell as an Analog Multiplier
708(3)
10.2.4 A Complete Analog Multiplier
711(1)
10.2.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector
712(4)
10.3 Phase-Locked Loops (PLL)
716(15)
10.3.1 Phase-Locked Loop Concepts
716(2)
10.3.2 The Phase-Locked Loop in the Locked Condition
718(9)
10.3.3 Integrated-Circuit Phase-Locked Loops
727(4)
10.4 Nonlinear Function Synthesis
731(5)
Chapter 11 Noise in Integrated Circuits
736(60)
11.1 Introduction
736(1)
11.2 Sources of Noise
736(8)
11.2.1 Shot Noise
736(4)
11.2.2 Thermal Noise
740(1)
11.2.3 Flicker Noise (1//Noise)
741(1)
11.2.4 Burst Noise (Popcorn Noise)
742(1)
11.2.5 Avalanche Noise
743(1)
11.3 Noise Models of Integrated-Circuit Components
744(4)
11.3.1 Junction Diode
744(1)
11.3.2 Bipolar Transistor
745(1)
11.3.3 MOS Transistor
746(1)
11.3.4 Resistors
747(1)
11.3.5 Capacitors and Inductors
747(1)
11.4 Circuit Noise Calculations
748(8)
11.4.1 Bipolar Transistor Noise Performance
750(4)
11.4.2 Equivalent Input Noise and the Minimum Detectable Signal
754(2)
11.5 Equivalent Input Noise Generators
756(8)
11.5.1 Bipolar Transistor Noise Generators
757(5)
11.5.2 MOS Transistor Noise Generators
762(2)
11.6 Effect of Feedback on Noise Performance
764(7)
11.6.1 Effect of Ideal Feedback on Noise Performance
764(1)
11.6.2 Effect of Practical Feedback on Noise Performance
765(6)
11.7 Noise Performance of Other Transistor Configurations
771(5)
11.7.1 Common-Base Stage Noise Performance
771(2)
11.7.2 Emitter-Follower Noise Performance
773(1)
11.7.3 Differential-Pair Noise Performance
773(3)
11.8 Noise in Operational Amplifiers
776(6)
11.9 Noise Bandwidth
782(4)
11.10 Noise Figure and Noise Temperature
786(10)
11.10.1 Noise Figure
786(4)
11.10.2 Noise Temperature
790(6)
Chapter 12 Fully Differential Operational Amplifiers
796(75)
12.1 Introduction
796(1)
12.2 Properties of Fully Differential Amplifiers
796(3)
12.3 Small-Signal Models for Balanced Differential Amplifiers
799(5)
12.4 Common-Mode Feedback
804(7)
12.4.1 Common-Mode Feedback at Low Frequencies
805(5)
12.4.2 Stability and Compensation Considerations in a CMFB Loop
810(1)
12.5 CMFB Circuits
811(12)
12.5.1 CMFB Using Resistive Divider and Amplifier
812(4)
12.5.2 CMFB Using Two Differential Pairs
816(3)
12.5.3 CMFB Using Transistors in the Triode Region
819(2)
12.5.4 Switched-Capacitor CMFB
821(2)
12.6 Fully Differential Op Amps
823(15)
12.6.1 A Fully Differential Two-Stage Op Amp
823(10)
12.6.2 Fully Differential Telescopic Cascode Op Amp
833(1)
12.6.3 Fully Differential Folded-Cascode Op Amp
834(1)
12.6.4 A Differential Op Amp with Two Differential Input Stages
835(1)
12.6.5 Neutralization
835(3)
12.7 Unbalanced Fully Differential Circuits
838(6)
12.8 Bandwidth of the CMFB Loop
844(1)
12.9 Analysis of a CMOS Fully Differential Folded-Cascode Op Amp
845(26)
12.9.1 DC Biasing
848(2)
12.9.2 Low-Frequency Analysis
850(6)
12.9.3 Frequency and Time Responses in a Feedback Application
856(15)
Index 871
Paul R. Gray received the BS, MS, and PhD degrees from the University of Arizona. He joined the University of California, Berkeley in 1971 with the Department of Electrical Engineering and Computer Sciences.Gray's research interests include bipolar and MOS circuit design, electro thermal interactions in integrated circuits, device modeling, telecommunications circuits, and analog-digital interfaces on analog integrated circuits. He is a member of numerous engineering and computer science organizations and is highly regarded in the field. Gray also holds several prizes, including the IEEE R.W.G. Baker Prize, IEEE Morris K Liebman award, IEEE Solid-State Circuits award, and many more.