This book provides a complete overview of significant design challenges in respect to circuit miniaturization and power reduction of the neural recording system, along with circuit topologies, architecture trends, and (post-silicon) circuit optimization algorithms. The introduced novel circuits for signal conditioning, quantization, and classification, as well as system configurations focus on optimized power-per-area performance, from the spatial resolution (i.e. number of channels), feasible wireless data bandwidth and information quality to the delivered power of implantable system.
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1 | (16) |
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1.1 Brain-Machine Interface: Circuits and Systems |
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2 | (4) |
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1.2 Remarks on Current Design Practice |
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6 | (6) |
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12 | (1) |
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1.4 Organization of the Book |
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13 | (4) |
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14 | (3) |
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2 Neural Signal Conditioning Circuits |
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17 | (16) |
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17 | (1) |
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2.2 Power-Efficient Neural Signal Conditioning Circuit |
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18 | (3) |
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2.3 Operational Amplifiers |
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21 | (6) |
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27 | (3) |
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30 | (3) |
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31 | (2) |
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3 Neural Signal Quantization Circuits |
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33 | (44) |
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33 | (1) |
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3.2 Low-Power A/D Converter Architectures |
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34 | (5) |
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3.3 A/D Converter Building Blocks |
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39 | (13) |
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3.3.1 Sample and Hold Circuit |
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39 | (4) |
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3.3.2 Bootstrap Switch Circuit |
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43 | (2) |
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3.3.3 Operational Amplifier Circuit |
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45 | (1) |
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3.3.4 Latched Comparator Circuit |
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46 | (6) |
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3.4 Voltage-Domain SAR A/D Conversion |
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52 | (6) |
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3.5 Current-Domain SAR A/D Conversion |
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58 | (2) |
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3.6 Time-Domain Two-Step A/D Conversion |
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60 | (5) |
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65 | (4) |
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69 | (8) |
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70 | (7) |
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4 Neural Signal Classification Circuits |
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77 | (18) |
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77 | (2) |
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79 | (2) |
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81 | (5) |
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86 | (5) |
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91 | (4) |
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91 | (4) |
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5 Brain-Machine Interface: System Optimization |
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95 | (30) |
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95 | (2) |
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5.2 Circuit Parameters Formulation |
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97 | (5) |
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5.2.1 Random Process Variability |
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97 | (4) |
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5.2.2 Noise in Neural Recording Interface |
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101 | (1) |
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5.3 Stochastic MNA for Process Variability Analysis |
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102 | (4) |
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5.4 Stochastic MNA for Noise Analysis |
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106 | (4) |
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5.5 PPA Optimization of Multichannel Neural Recording Interface |
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110 | (3) |
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110 | (2) |
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5.5.2 Power Per Area Optimization |
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112 | (1) |
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113 | (6) |
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119 | (6) |
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120 | (5) |
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125 | (6) |
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6.1 Summary of the Results |
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125 | (3) |
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6.2 Recommendations and Future Research |
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128 | (3) |
| Appendix |
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131 | (30) |
| Index |
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161 | |
Amir Zjajo received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000 and the PhD. degree from Eindhoven University of Technology, Eindhoven, The Netherlands in 2010, all in electrical engineering. In 2000, he joined Philips Research Laboratories as a member of the research staff in the Mixed-Signal Circuits and Systems Group. From 2006 until 2009, he was with Corporate Research of NXP Semiconductors as a Senior Research Scientist. In 2009, he joined Delft University of Technology as a faculty member in Circuits and Systems group.
Dr. Zjajo has published more than 70 papers in referenced journals and conference proceedings, and holds more than 10 US patents or patent pending. He is the author of the books Low-Voltage High-Resolution A/D Converters: Design,Test and Calibration (Springer, 2011, Chinese translation, China Machine Press, 2015), and Stochastic Process Variations in Deep-Submicron CMOS: Circuits and Algorithms (Springer,2014). He serves as a member of Technical Program Committee of IEEE Design, Automation and Test in Europe Conference, IEEE International Symposium on Circuits and Systems, IEEE International Symposium on VLSI, IEEE International Symposium on Nanoelectronic and Information Systems, and IEEE International Conference on Embedded Computer Systems.
His research interests include power-efficient mixed-signal circuit and system design for health and mobile applications, and neuromorphic electronic circuits for autonomous cognitive systems. Dr. Zjajo won the best paper award at BIODEVICES 2015, and DATE 2012.
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