This book enables readers to design effective ESD protection solutions for all mainstream RF fabrication processes (GaAs pHEMT, SiGe HBT, CMOS). The new techniques introduced by the authors have much higher protection levels and much lower parasitic effects than those of existing ESD protection devices. The authors describe in detail the ESD phenomenon, as well as ESD protection fundamentals, standards, test equipment, and basic design strategies. Readers will benefit from realistic case studies of ESD protection for RFICs and will learn to increase significantly modern RFICs ESD safety level, while maximizing RF performance.
Introduction.- Basics in ESD Protection of RF IC s.- On-Chip RF ESD Protection Solution in Standard CMOS Process.- On-Chip RF ESD Protection Solution in SiGe BiCMOS Process.- On-Chip RF ESD Protection Solution in GaAs pHEMT Process.- Conclusion.
| 1 Basics in ESD Protection of Radio Frequency Integrated Circuits |
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1 | (12) |
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1.1 ESD Models and Test Setup |
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2 | (3) |
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1.2 On-Chip ESD Design Concepts and Design Windows |
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5 | (5) |
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1.2.1 Characteristics of ESD Protection Devices |
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6 | (2) |
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1.2.2 Typical On-Chip ESD Protection Devices for Radio Frequency Integrated Circuits |
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8 | (2) |
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1.3 Special Challenge of ESD Protection in Radio Frequency Integrated Circuits |
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10 | (1) |
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11 | (2) |
| 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process |
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13 | (10) |
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13 | (1) |
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2.2 ESD Protection Strategy of CMOS RF ICs |
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14 | (2) |
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2.3 High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for Radio Frequency Protection |
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16 | (5) |
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16 | (2) |
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2.3.2 Measurements and Discussion |
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18 | (3) |
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21 | (2) |
| 3 Design of SiGe SCR Devices for Radio Frequency Integrated Circuits in SiGe BiCMOS Process |
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23 | (20) |
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3.1 Introduction of SCR Device Technology |
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23 | (3) |
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3.2 An Improved Vertical SCR-Based ESD Protection Design |
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26 | (10) |
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26 | (1) |
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3.2.2 Measurements and Discussion |
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27 | (9) |
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3.3 Optimization of ESD Protection for High Speed SiGe Applications |
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36 | (6) |
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3.3.1 Capacitance Analysis |
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36 | (2) |
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3.3.2 ESD Devices for On-chip RF Integration |
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38 | (1) |
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3.3.3 ESD Protection in RF PADS Configuration: Schematic Applications |
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38 | (1) |
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3.3.4 ESD Protection in Reference RF Circuit Schemes Using SiGe SCR |
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38 | (4) |
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42 | (1) |
| 4 On-Chip Radio Frequency ESD Protection Solution in GaAs pHEMT Process |
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43 | (38) |
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4.1 Failure Analysis of Conventional Single-Gate pHEMT-Based ESD Protection Clamp |
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43 | (14) |
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4.1.1 pHEMT Clamp Technology Computer-Aided Design (TCAD) Setup for Failure Analysis |
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43 | (4) |
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47 | (2) |
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4.1.3 Postsnapback Saturation Behavior |
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49 | (5) |
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4.1.4 Thermal Failure Behavior |
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54 | (3) |
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4.2 Multigate E-Mode pHEMT-Based ESD Protection Clamp |
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57 | (13) |
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59 | (2) |
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4.2.2 Measurements and Discussion |
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61 | (9) |
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4.3 Multigate D-Mode pHEMT-Based ESD Protection Clamp |
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70 | (6) |
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71 | (2) |
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4.3.2 Measurements and Discussion |
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73 | (3) |
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4.4 Drain-Less pHEMT-Based ESD Protection Clamp |
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76 | (4) |
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76 | (2) |
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4.4.2 Measurements and Discussion |
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78 | (2) |
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80 | (1) |
| 5 Conclusion |
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81 | (2) |
| References |
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Dr. Qiang Cui received his B.S, M.S and PhD in Electrical Engineering in 2006, 2008, 2013 respectively. His research work includes Radio Frequency Integrated Circuits (RFIC) Design and Reliability. His research work has been referenced in publications and also applied to industry application. He is now a senior RF IC design engineer in RF Micro Devices (RFMD).
Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. He is now with the School of EECS at the University of Central Florida (UCF). His current research interests are electrostatic discharge (ESD) protection design, modeling, and simulation. Dr. Liou has been awarded 8 U.S. patents, and has published 10 books, 2 book chapter, more than 270 journal papers, and more than 220 papers in international and national conference proceedings. Dr. Liou was awarded the UCF Pegasus Distinguished Professor in 2009 the highest honor bestowed to a faculty member at UCF, UCF Distinguished Researcher Award in 1992, 1998, 2002, and 2009, and IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award in 2004. His other honors are Fellow of IEEE, Fellow of IET, Fang Chia Chair Professor of Fang Chia University, Taiwan, and Chang Jiang Endowed Professor of Ministry of Education, China the highest honorary professorship in China.
Dr. Javier A. Salcedo is a Technology Development Engineer at Analog Devices (ADI), Wilmington, Massachusetts. Dr. Salcedos technical publications and inventions in electron devices technology are regularly referenced in the literature and have been adopted in the semiconductor industry to enable new IC applications for consumer electronics, communication infrastructure, healthcare systems, automotive electronics and industrial control applications. Dr. Salcedo is a recipient of the Institute of Electrical and Electronics Engineers (IEEE)Electron Devices Society (EDS) Ph.D. Fellowship, member of the American Association for the Advancement of Science (AAAS), member of the Electrostatic Discharge Association (ESDA) and a Senior Member of the IEEE.
