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E-grāmata: Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures

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  • Formāts: PDF+DRM
  • Izdošanas datums: 20-Dec-2019
  • Izdevniecība: Springer Nature Switzerland AG
  • Valoda: eng
  • ISBN-13: 9783030313104
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Design and Test Strategies for 2D/3D Integration for NoC-based Multicore ArchitecturesPalielināt
  • Formāts: PDF+DRM
  • Izdošanas datums: 20-Dec-2019
  • Izdevniecība: Springer Nature Switzerland AG
  • Valoda: eng
  • ISBN-13: 9783030313104
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This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.  It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.  

  • Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;
  • Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;
  • Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.


1 Introduction
1(12)
1 System-on-Chip to Network-on-Chip: A Paradigm Shift
1(2)
2 NoC-Based Multi-Core Systems with Three-Dimensional (3D) Integration Technology
3(1)
3 Power and Temperature Issues in NoC-Based Multi-Core Systems
4(1)
4 Testing of NoC-Based Multi-Core Systems
5(1)
5 Issues in Multi-Core Systems Design with Integrated NoC and 3D Technologies
6(1)
6 Application Mapping and TSV Placement: A Combined Approach
7(1)
7 Swarm Based Optimizer
8(1)
8 Scope and Motivation of the Works
9(1)
9 Summary of This Book
9(1)
10 Conclusion
10(1)
References
11(2)
2 Alternative Approaches
13(20)
1 Application Mapping Techniques
14(1)
1.1 Dynamic Application Mapping Techniques
14(1)
2 Static Application Mapping Techniques
15(6)
2.1 Exact Application Mapping Techniques
16(1)
2.2 Search-Based Application Mapping Techniques
16(5)
3 Application Mapping Together with TSV Placement for 3D NoC-Based Multi-Core Systems
21(2)
4 Thermal Management Techniques for NoC-Based Multi-Core Systems
23(2)
5 Thermal-Aware Testing of NoC-Based Multi-Core Systems
25(1)
6 Conclusion
26(1)
References
26(7)
3 Iterative Application Mapping with TSV Placement Strategy for Design a 3D NoC-Based Multi-Core Systems
33(20)
1 3D NoC-Based Systems and Routing Algorithm
35(1)
2 TSV Placement and Application Mapping Strategy
36(1)
3 Partitioning Algorithm
37(2)
4 Application Mapping onto Mesh-Based 3D NoC Systems
39(3)
4.1 Initial Mapping Phase
40(1)
4.2 Iterative Improvement Phase
40(2)
5 Experimental Results and Analysis
42(9)
5.1 Results on Different TSV Distributions and Mapping Strategies
44(3)
5.2 Impact of TSV Position Selection
47(1)
5.3 Dynamic Performance of Different Mapping and TSV Configurations
48(3)
6 Conclusion
51(1)
References
51(2)
4 A Constructive Heuristic for Designing a 3D NoC-Based Multi-Core Systems
53(12)
1 Proposed Heuristic for TSV Placement and Application Mapping
53(4)
1.1 Algorithm Philosophy
54(3)
2 Experimental Results and Analysis
57(6)
2.1 Results on Different TSV Distributions and Mapping Strategies
57(1)
2.2 Impact of TSV Position Selection
57(3)
2.3 Dynamic Performance of Different Mapping and TSV Configurations
60(3)
3 Conclusion
63(1)
References
63(2)
5 A Discrete Particle Swarm Optimization Technique for Designing a 3D NoC-Based Multi-Core Systems
65(22)
1 ILP Formulation for TSV Placement and Application Mapping
66(3)
1.1 Objective Function
66(1)
1.2 Constraints
67(2)
2 PSO Formulation for TSV Placement and Application Mapping
69(8)
2.1 Particle Formulation and Fitness Function
70(3)
2.2 Augmentation to the Basic PSO
73(2)
2.3 PSO-Based Application Mapping and TSV Placement Algorithm
75(2)
3 Experimental Results and Analysis
77(7)
3.1 Communication Cost Comparison Between ILP and PSO
77(1)
3.2 Impact of Initial Population Generation
77(1)
3.3 Effect of Inversion Mutation (IM) and Random Number Generator
78(1)
3.4 Comparison with Existing Works
78(1)
3.5 Dynamic Evaluation of Proposed Solutions
79(5)
4 Conclusion
84(1)
References
84(3)
6 Thermal-Aware Application Mapping Strategy for Designing a 2D NoC-Based Multi-Core Systems
87(24)
1 Temperature Calculation
88(1)
2 ILP Formulation for Thermal-Aware Mapping
89(3)
2.1 Objective Function
90(1)
2.2 Constraints
91(1)
3 PSO Formulation for Thermal-Aware Mapping
92(6)
3.1 Particle Formulation and Fitness Calculation
92(1)
3.2 Augmentation to the Basic PSO
93(3)
3.3 PSO-Based Thermal-Aware Mapping Technique
96(2)
4 Experimental Results and Analysis
98(9)
4.1 Comparison Across Mapping Techniques
98(1)
4.2 Effect of Inversion Mutation (IM) and Randomness on the Augmentation of Basic PSO
99(2)
4.3 Comparison with Other Methods
101(1)
4.4 Dynamic Performance Comparison
101(2)
4.5 Trading-Off Peak Temperature and Communication Cost
103(3)
4.6 Imposing Thermal Safety
106(1)
4.7 Experimentation with Big Data and Graph Analytical Workloads
106(1)
5 Conclusion
107(1)
References
108(3)
7 Thermal-aware Design Strategies for the 3D NoC-based Multi-Core Systems
111(14)
1 Proposed Techniques
112(1)
2 Temperature Calculation
112(1)
3 Thermal-Aware 3D Application Mapping
113(4)
3.1 PSO Formulation
113(4)
4 Thermal-Aware 3D NoC Design Using Thermal-Vias
117(1)
4.1 PSO Formulation
118(2)
5 Experimental Results
120(2)
5.1 Thermal-Aware 3D NoC-Based Systems Design with the Application Mapping Strategy
121(1)
5.2 Thermal-Aware 3D NoC-Based Systems Design Using Thermal Vias
121(1)
6 Conclusion
122(1)
References
123(2)
8 Thermal-Aware Test Strategies for NoC-Based Multi-Core Systems
125(28)
1 Testtime and Temperature Calculation
126(2)
2 Problem Formulation of Preemptive Test Scheduling
128(1)
3 ILP Formulation for Preemptive Test Scheduling
129(8)
3.1 Pools Structure
129(2)
3.2 Objective Function
131(1)
3.3 Constraints
132(5)
4 PSO Formulation for Preemptive Test Scheduling
137(3)
4.1 Particle Structure and Fitness
137(1)
4.2 Evolution Process
138(1)
4.3 Augmentation to the Basic PSO
138(2)
5 PSO for Thermal-Aware Preemptive Test Scheduling
140(1)
6 Experimental Results
141(10)
6.1 Experimental Setup
141(1)
6.2 Testtime Comparison Between ILP and PSO
142(1)
6.3 Effect of Inversion Mutation (IM) and Randomness into the Basic PSO
143(1)
6.4 Impact of Multiple PSOs
143(1)
6.5 Testtime Comparison with Non-Preemptive Method
144(1)
6.6 Trading-Off Between Peak Temperature and Testtime
144(1)
6.7 Comparison with Other Methods
145(1)
6.8 Thermal-Aware Test Scheduling for 3D NoC-Based Systems
146(5)
7 Conclusion
151(1)
References
151(2)
9 Conclusion and Future Works
153(4)
1 Conclusion
153(1)
2 Possible Future Works
154(3)
Index 157
Kanchan Manna is currently an assistant professor in Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Patna, India. Prior to this, he has worked as a post-doctoral scientist in the Department of Electrical and Computer Engineering (ECE) at George Washington University (GWU), Washington-DC, USA. He earned the MS degree in information technology from Indian Institute of Technology (IIT) Kharagpur, India and the PhD degree in computer science engineering from IIT Kharagpur. His current research interests include Network-on-Chip (NoC) based multicore architecture design, performance and cost evaluation, application mapping in 2D and 3D environments, including thermal-safety, reliability, fault-tolerant and testing.





 





Jimson Mathew is currently an associate professor and head of the Computer Science and Engineering Department, Indian Institute of Technology (IIT) Patna, India. He is also honorary visiting fellow at the Department of Computer Science and Engineering, University of Bristol, UK. He received the Masters in Computer engineering from Nanyang Technological University, Singapore and the Ph.D. degree in computer engineering from the University of Bristol, Bristol, U.K. Prior to this, he has worked with the Centre for Wireless Communications, National University of Singapore, Bell Laboratories Research Lucent Technologies North Ryde, Australia, Royal Institute of Technology KTH, Stockholm, Sweden and Department of Computer Science, University of Bristol, UK. His research interests include fault-tolerant computing, computer arithmetic, hardware security, very large scale integration design and design automation, and design of Network on Chip Architectures. He is the co-author of three published books, and close to 100 publications in international journals and conferences of repute.
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