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E-grāmata: Digital System Design using FSMs: A Practical Learning Approach

(Northumbria University, UK)
  • Formāts: EPUB+DRM
  • Izdošanas datums: 23-Jun-2021
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9781119782728
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Digital System Design using FSMs: A Practical Learning ApproachPalielināt
  • Formāts: EPUB+DRM
  • Izdošanas datums: 23-Jun-2021
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9781119782728
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DIGITAL SYSTEM DESIGN USING FSMS Explore this concise guide perfect for digital designers and students of electronic engineering who work in or study embedded systems

Digital System Design using FSMs: A Practical Learning Approach delivers a thorough update on the authors earlier work, FSM-Based Digital Design using Verilog HDL. The new book retains the foundational content from the first book while including refreshed content to cover the design of Finite State Machines delivered in a linear programmed learning format. The author describes a different form of State Machines based on Toggle Flip Flops and Data Flip Flops.

The book includes many figures of which 15 are Verilog HDL simulations that readers can use to test out the design methods described in the book, as well as 19 Logisim simulation files with figures. Additional circuits are also contained within the Wiley web folder. It has tutorials and exercises, including comprehensive coverage of real-world examples demonstrated alongside the frame-by-frame presentations of the techniques used.

In addition to covering the necessary Boolean algebra in sufficient detail for the reader to implement the FSM based systems used in the book, readers will also benefit from the inclusion of:





A thorough introduction to finite-state machines and state diagrams for the design of electronic circuits and systems An exploration of using state diagrams to control external hardware subsystems Discussions of synthesizing hardware from a state diagram, synchronous and asynchronous finite-state machine designs, and testing finite-state machines using a test-bench module A treatment of the One Hot Technique in finite-state machine design An examination of Verilog HDL, including its elements An analysis of Petri-Nets including both sequential and parallel system design

Suitable for design engineers and senior technicians seeking to enhance their skills in developing digital systems, Digital System Design using FSMs: A Practical Learning Approach will also earn a place in the libraries of undergraduate and graduate electrical and electronic engineering students and researchers.
Preface viii
Acknowledgements x
About the Companion Website xi
Guide to Supplementary Resources xii
1 Introduction to Finite State Machines
1(24)
1.1 Some Notes on Style
1(24)
2 Using FSMs to Control External Devices
25(20)
2.1 Introduction
25(20)
3 Introduction to FSM Synthesis
45(52)
3.1 Introduction
45(26)
3.2 Tutorials Covering
Chapters 1, 2, and 3
71(26)
3.2.1 Binary data serial transmitter FSM
71(5)
3.2.2 The high low FSM system
76(4)
3.2.3 The clocked watchdog timer FSM
80(1)
3.2.3.1 FSM equations
81(3)
3.2.4 The asynchronous receiver system clocked FSM
84(2)
3.2.4.1 Brief note on the development of the test bench generator
86(1)
3.2.4.2 The state diagram
86(1)
3.2.4.3 The state diagram equations
87(1)
3.2.4.4 The outputs
87(8)
3.2.4.5 Verilog HDL simulation of the completed system
95(2)
4 Asynchronous FSM Methods
97(56)
4.1 Introduction to Asynchronous FSM
97(47)
4.2 Summary
144(1)
4.3 Tutorials
144(9)
4.3.1 FSM motor with fault detection
144(4)
4.3.2 The mower in four and two states
148(5)
5 Clocked One Hot Method of FSM Design
153(26)
5.1 Introduction
153(15)
5.2 Tutorials on the Clocked One Hot FSM Method
168(11)
5.2.1 Seven-state system clocked one hot method
168(2)
5.2.2 Memory tester FSM
170(4)
5.2.3 Eight-bit sequence detector FSM
174(5)
6 Further Event-Driven FSM Design
179(18)
6.1 Introduction
179(16)
6.2 Conclusions
195(2)
7 Petri Net FSM Design
197(54)
7.1 Introduction
197(37)
7.2 Tutorials Using Petri Net FSM
234(15)
7.2.1 Controlled shared resource Petri nets
234(6)
7.2.2 Serial clock-driven Petri net FSM
240(7)
7.2.3 Using asynchronous (event-driven) design with Petri nets
247(2)
7.3 Conclusions
249(2)
Appendix A1 Boolean Algebra
251(10)
A1.1 Basic Gate Symbols
251(1)
A1.2 The Exclusive OR and Exclusive NOR
252(1)
A1.3 Laws of Boolean Algebra
252(5)
A1.3.1 Basic OR rules
252(1)
A1.3.2 Basic AND rules
253(1)
A1.3.3 Associative and commutative laws
253(1)
A1.3.4 Distributive laws
253(1)
A1.3.5 Auxiliary rule for static 1 hazard removal
254(1)
A1.3.5.1 Proof of the Auxiliary Rule
254(1)
A1.3.6 Consensus theorem
254(1)
A1.3.7 The effect of signal delay in logic gates
255(1)
A1.3.8 De-Morgan's theorem
256(1)
A1.4 Examples of Applying the Laws of Boolean Algebra
257(1)
A1.4.1 Converting AND-OR to NAND
257(1)
A1.4.2 Converting AND-OR to NOR
257(1)
A1.4.3 Logical adjacency rule
258(1)
A1.5 Summary
258(3)
Appendix A2 Use of Verilog HDL and Logisim to FSM
261(24)
A2.1 The Single-Pulse Generator with Memory Clock-Driven FSM
261(6)
A2.2 Test Bench Module and its Purpose
267(1)
A2.3 Using Synapticad Software
268(2)
A2.4 More Direct Method
270(1)
A2.5 A Very Simple Guide to Using the Logisim Simulator
271(1)
A2.5.1 The Logisim top level menu items
271(2)
A2.6 Using Flip-Flops in a Circuit
273(2)
A2.7 Example Single-Pulse FSM
275(3)
A2.8 How to Use the Simulator to Simulate the Single-Pulse FSM
278(1)
A2.8.1 Using Logisim with the truth table approach
278(1)
A2.9 Using Logisim with the Truth Table Approach
279(2)
A2.9.1 Useful note
281(1)
A2.10 Summary
281(4)
Appendix A3 Counters, Shift Registers, Input, and Output with an FSM
285(22)
A3.1 Basic Down Synchronous Binary Counter Development
285(3)
A3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops
288(3)
A3.3 Parallel Loading Counters - Using T Flip-Flops
291(1)
A3.4 Using D Flip-Flops To Build Parallel Loading Counters
292(1)
A3.5 Simple Binary Up Counter with Parallel Inputs
293(1)
A3.6 Clock Circuit to Drive the Counter (and FSM)
294(1)
A3.7 Counter Design Using Don't Care States
295(1)
A3.8 Shift Registers
296(2)
A3.9 Dealing with Input and Output Signals Using FSM
298(3)
A3.10 Using Logisim to Work with Larger FSM Systems
301(1)
A3.10.1 The equations
302(3)
A3.11 Summary
305(2)
Appendix A4 Finite State Machines Using Verilog Behavioural Mode
307(10)
A4.1 Introduction
307(1)
A4.2 The Single-Pulse/Multiple-Pulse Generator with Memory FSM
307(6)
A4.3 The Memory Tester FSM Revisited
313(2)
A4.4 Summary
315(2)
Appendix A5 Programming a Finite State Machine
317(12)
A5.1 Introduction
317(1)
A5.2 The Parallel Loading Counter
317(2)
A5.3 The Multiplexer
319(1)
A5.4 The Micro Instruction
320(1)
A5.5 The Memory
320(1)
A5.6 The Instruction Set
321(2)
A5.7 Simple Example: Single-Pulse FSM
323(2)
A5.8 The Final Example
325(3)
A5.9 The Program Code
328(1)
A5.10 Returning Unused States via Other Transition Paths
328(1)
A5.11 Summary
328(1)
Appendix A6 The Rotational Detector Using Logisim Simulator with Sub-Circuits
329(6)
A6.1 Using the Two-State Diagram Arrangement
333(2)
Bibliography 335(2)
Index 337
Peter D. Minns, PhD, now retired, has over 33 years experience as an academic Senior Lecturer, most recently in the Department of Mathematics, Physics, and Electrical Engineering at Northumbria University at Newcastle, UK. Prior to academia, he worked in the telecommunications industry and in Power System Protection as a Design and Development Engineer.
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