Atjaunināt sīkdatņu piekrišanu

Efficient Test Methodologies for High-Speed Serial Links 2010 ed. [Hardback]

,
  • Formāts: Hardback, 98 pages, height x width: 235x155 mm, weight: 750 g, XII, 98 p., 1 Hardback
  • Sērija : Lecture Notes in Electrical Engineering 51
  • Izdošanas datums: 07-Dec-2009
  • Izdevniecība: Springer
  • ISBN-10: 9048134420
  • ISBN-13: 9789048134427
Citas grāmatas par šo tēmu:
  • Hardback
  • Cena: 122,77 €*
  • * ši ir gala cena, t.i., netiek piemērotas nekādas papildus atlaides
  • Standarta cena: 144,44 €
  • Ietaupiet 15%
  • Grāmatu piegādes laiks ir 3-4 nedēļas, ja grāmata ir uz vietas izdevniecības noliktavā. Ja izdevējam nepieciešams publicēt jaunu tirāžu, grāmatas piegāde var aizkavēties.
  • Daudzums:
  • Ielikt grozā
  • Piegādes laiks - 4-6 nedēļas
  • Pievienot vēlmju sarakstam
Efficient Test Methodologies for High-Speed Serial Links 2010 ed.Palielināt
  • Formāts: Hardback, 98 pages, height x width: 235x155 mm, weight: 750 g, XII, 98 p., 1 Hardback
  • Sērija : Lecture Notes in Electrical Engineering 51
  • Izdošanas datums: 07-Dec-2009
  • Izdevniecība: Springer
  • ISBN-10: 9048134420
  • ISBN-13: 9789048134427
Citas grāmatas par šo tēmu:
Permanent link: https://www.kriso.lv/db/9789048134427.html
Keywords:
Covering new and promising techniques for cost-effectively testing high-speed interfaces with high test coverage, the authors focus on efficient test methodologies for jitter and bit-error-rate, widely used for assessing the quality of communication systems.

Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
1 Introduction 1
1.1 Overview of High-Speed Serial Links
1
1.1.1 High-Speed Serial Link System
1
1.1.2 Testing High-Speed Serial Links
2
1.2 Challenges in Testing High-Speed Serial Links
3
1.3 Contributions of the Dissertation
4
2 An Efficient Jitter Measurement Technique 7
2.1 Comparator Undersampling Technique
7
2.2 Random Jitter Measurement
9
2.2.1 Proposed RI Measurement Technique
10
2.2.2 Limitations of the Technique
12
2.3 Experimental Results
13
2.3.1 Simulation Results
14
2.3.2 Measurement Results
16
2.4 Summary
18
3 BER Estimation for Linear Clock and Data Recovery Circuit 19
3.1 BER Analysis with Random Jitter
20
3.1.1 Error Occurrences
20
3.1.2 BER Estimation with Random Jitter
20
3.2 BER Analysis with Random Jitter and Periodic Jitter
22
3.2.1 Jitter Transfer Characteristics of a CDR Circuit
23
3.2.2 BER Estimation with RJ and PJ
25
3.3 BER Analysis Including Intrinsic Noise in the CDR Circuit
32
3.4 Experimental Results
34
3.4.1 Simulation Results
34
3.4.2 Hardware Validation Results
35
3.5 Summary and Future Work
40
4 BER Estimation for Non-linear Clock and Data Recovery Circuit 41
4.1 Jitter Analysis for BB CDR Circuits
41
4.1.1 Jitter Transfer Analysis
42
4.1.2 Jitter Tolerance Analysis
45
4.2 BER Estimation
45
4.2.1 Variation of Jitter Transfer Due to RJ
46
4.2.2 BER Estimation
48
4.3 Experimental Setup and Results
49
4.3.1 Simulation Setup
49
4.3.2 Simulation Results
50
4.4 Summary
51
5 Gaps in Timing Margining Test 53
5.1 Timing Margining Test Basics
53
5.2 Gap Analysis in Timing Margining Test
54
5.2.1 Random Jitter
55
5.2.2 PLL-Based Clock Recovery with Non-linear Phase Detector
56
5.2.3 Jitter Amplification
59
5.2.4 Duty Cycle Distortion in Clock
61
5.3 Summary and Future Work
63
6 An Accurate Jitter Estimation Technique 65
6.1 Characteristics of DJ
65
6.1.1 ISI-Induced Jitter
66
6.1.2 Crosstalk-Induced Jitter
66
6.2 Total Jitter Estimation
68
6.2.1 Estimation Based on Dual-Dirac Model
68
6.2.2 High-Order Polynomial Fitting
71
6.2.3 Accuracy Versus Number of Samples for Fitting
71
6.3 Summary
72
7 A Two-Tone Test Method for Continuous-Time Adaptive Equalizers 75
7.1 Continuous-Time Adaptive Equalizer
76
7.2 Proposed Two-Tone Test Method
78
7.2.1 Description of the Test Method
78
7.2.2 Implementation of the Test Method
79
7.3 Experimental Results
82
7.3.1 MATLAB Simulation Results
82
7.3.2 Transistor-Level Simulation Results
84
7.4 Summary and Future Work
85
8 Conclusions 89
A Extracting Effective PJ and RJ Components from Jitter Histogram 91
References 95