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Part I Multimedia Systems |
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3 | (8) |
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3 | (3) |
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1.2 Embedded Systems and Reconfigurable Architectures |
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6 | (2) |
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8 | (3) |
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2 Advances in Multimedia Encryption |
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11 | (12) |
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11 | (1) |
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2.2 Multimedia Encryption Problem |
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12 | (1) |
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2.3 Common Approaches to Video Encryption |
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13 | (10) |
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13 | (4) |
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2.3.2 Post-compression Encryption Algorithm |
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17 | (2) |
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2.3.3 Pre-compression Encryption Algorithm |
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19 | (1) |
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2.3.4 Selective Encryption |
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19 | (2) |
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2.3.5 Joint Video Compression and Encryption (JVCE) Approaches |
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21 | (1) |
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2.3.6 Future of JVCE Schemes |
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21 | (1) |
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22 | (1) |
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3 Securing Multimedia Content Using Joint Compression and Encryption |
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23 | (10) |
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23 | (1) |
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24 | (2) |
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26 | (7) |
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28 | (5) |
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4 Polymorphic Wavelet Transform |
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33 | (34) |
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33 | (4) |
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4.2 Motivation and Insight |
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37 | (3) |
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4.2.1 Daubechies 9/7-Tap Bi-orthogonal Filter |
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38 | (1) |
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4.2.2 Le Gall's 5/3 Filter |
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39 | (1) |
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4.3 Background and Related Work |
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40 | (3) |
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4.3.1 Wavelet Transform Background |
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41 | (1) |
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4.3.2 Hardware Implementation of DWT |
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42 | (1) |
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43 | (8) |
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4.4.1 Parameterized Filter Design |
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43 | (1) |
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44 | (1) |
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45 | (2) |
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4.4.4 Hardware Architectures |
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47 | (4) |
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4.5 Fixed Point Implementation |
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51 | (1) |
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4.6 Hardware (Re)-allocation |
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52 | (3) |
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4.6.1 `On-the-Fly' Switching |
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52 | (2) |
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4.6.2 `Bit-Width' Switching |
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54 | (1) |
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55 | (7) |
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4.7.1 Image Reconstruction Quality |
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55 | (1) |
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4.7.2 Hardware vs. Software Performance |
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56 | (1) |
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4.7.3 Hardware Comparison |
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57 | (3) |
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4.7.4 Dynamic Bit Allocation |
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60 | (1) |
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4.7.5 Real-World Application |
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60 | (2) |
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4.8 Conclusions and Future Work |
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62 | (5) |
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62 | (5) |
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5 The Secure Wavelet Transform |
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67 | (24) |
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67 | (2) |
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69 | (7) |
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5.2.1 Parameterized Construction of DWT |
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70 | (4) |
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5.2.2 Subband Re-orientation |
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74 | (2) |
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76 | (3) |
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5.4 Hardware Implementation |
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79 | (5) |
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5.4.1 Reconfigurable Constant Multiplier (RCM) |
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80 | (4) |
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5.4.2 Implementation Results |
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84 | (1) |
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5.5 Parameterized Lifting |
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84 | (3) |
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5.6 Conclusion and Future Work |
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87 | (4) |
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87 | (4) |
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91 | (22) |
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91 | (3) |
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6.1.1 Chaos and Cryptography |
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91 | (1) |
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6.1.2 Wavelets and Chaotic Filter Banks |
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92 | (1) |
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6.1.3 Scope and Organization |
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93 | (1) |
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6.1.4 Reconfigurable Hardware Implementation of DWT |
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93 | (1) |
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6.2 Chaotic Filter Bank Scheme |
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94 | (2) |
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95 | (1) |
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95 | (1) |
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96 | (2) |
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6.4 Improved Chaotic Oscillator |
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98 | (2) |
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6.4.1 The Modified Logistic Map (MLM) |
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98 | (2) |
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6.5 Wavelet Parameterization |
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100 | (1) |
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6.6 Resistance of Chaotic Generator Against Cryptanalysis |
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100 | (5) |
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101 | (2) |
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103 | (1) |
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103 | (2) |
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105 | (1) |
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6.8 Hardware Implementation |
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106 | (3) |
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6.8.1 Hardware Optimizations for ICO |
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108 | (1) |
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109 | (4) |
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109 | (4) |
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7 Chaotic Arithmetic Coding |
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113 | (30) |
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113 | (2) |
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7.1.1 Weakness of SAC Coder |
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114 | (1) |
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7.2 Arithmetic Coding with Piece-wise Linear Chaotic Maps |
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115 | (6) |
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7.2.1 Compression Efficiency |
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117 | (1) |
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7.2.2 Binary Chaotic Arithmetic Coding (BCAC) |
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118 | (3) |
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7.2.3 Implementation Efficiency |
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121 | (1) |
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121 | (8) |
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7.3.1 Application to Multimedia/Data Encryption |
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121 | (1) |
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122 | (1) |
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7.3.3 Security Enhancements (SE) |
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122 | (3) |
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7.3.4 Resistance to Known Attacks |
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125 | (2) |
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7.3.5 Comparison with BAC+AES |
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127 | (1) |
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7.3.6 Key and Plaintext Sensitivity |
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127 | (2) |
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7.3.7 Selective Encryption Using BCAC |
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129 | (1) |
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129 | (1) |
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7.5 Hardware Implementation |
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130 | (7) |
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131 | (1) |
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7.5.2 Implementation Details |
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132 | (1) |
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7.5.3 Binary Arithmetic Coder (BAC) Architecture |
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133 | (1) |
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7.5.4 Binary Chaotic Arithmetic Coder and Encryption (BCAC) Architecture |
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133 | (1) |
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134 | (1) |
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7.5.6 N-ary Chaotic Arithmetic Coder and Encryption (NCAC) Coding |
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134 | (2) |
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7.5.7 Multiple Symbol per Cycle Arithmetic Coding |
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136 | (1) |
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137 | (3) |
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7.6.1 Multiple Huffman Tables |
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137 | (1) |
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7.6.2 Randomized Arithmetic Coding |
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138 | (1) |
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7.6.3 Secure Arithmetic Coding |
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139 | (1) |
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140 | (3) |
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140 | (3) |
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143 | (2) |
Index |
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145 | |