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E-grāmata: ESD: RF Technology and Circuits

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(IBM, USA)
  • Formāts: PDF+DRM
  • Izdošanas datums: 02-Nov-2006
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9780470061398
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ESD: RF Technology and CircuitsPalielināt
  • Formāts: PDF+DRM
  • Izdošanas datums: 02-Nov-2006
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9780470061398
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With the growth of high-speed telecommunications and wireless technology, it is becoming increasingly important for engineers to understand radio frequency (RF) applications and their sensitivity to electrostatic discharge (ESD) phenomena. This enables the development of ESD design methods for RF technology, leading to increased protection against electrical overstress (EOS) and ESD.

ESD: RF Technology and Circuits:

  • Presents methods for co-synthesizisng ESD networks for RF applications to achieve improved performance and ESD protection of semiconductor chips;
  • discusses RF ESD design methods of capacitance load transformation, matching network co-synthesis, capacitance shunts, inductive shunts, impedance isolation, load cancellation methods, distributed loads, emitter degeneration, buffering and ballasting;
  • examines ESD protection and design of active and passive elements in RF complementary metal-oxide-semiconductor (CMOS), RF laterally-diffused metal oxide semiconductor (LDMOS), RF BiCMOS Silicon Germanium (SiGe), RF BiCMOS Silicon Germanium Carbon (SiGeC), and Gallim Arsenide technology;
  • gives information on RF ESD testing methodologies, RF degradation effects, and failure mechanisms for devices, circuits and systems;
  • highlights RF ESD mixed-signal design integration of digital, analog and RF circuitry;
  • sets out examples of RF ESD design computer aided design methodologies;
  • covers state-of-the-art RF ESD input circuits, as well as voltage-triggered to RC-triggered ESD power clamps networks in RF technologies, as well as off-chip protection concepts.

Following the authors series of books on ESD, this book will be a thorough overview of ESD in RF technology for RF semiconductor chip and ESD engineers. Device and circuit engineers working in the RF domain, and quality, reliability and failure analysis engineers will also find it a valuable reference in the rapidly growing are of RF ESD design. In addition, it will appeal to graduate students in RF microwave technology and RF circuit design.

Preface xv
Acknowledgements xxi
Chapter 1 RF DESIGN and ESD 1(60)
1.1 Fundamental Concepts of ESD Design
1(3)
1.2 Fundamental Concepts of RF ESD Design
4(6)
1.3 Key RF ESD Contributions
10(3)
1.4 Key RF ESD Patents
13(1)
1.5 ESD Failure Mechanisms
13(4)
1.5.1 RF CMOS ESD Failure Mechanisms
14(1)
1.5.2 Silicon Germanium ESD Failure Mechanisms
15(1)
1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices
15(1)
1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms
16(1)
1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms
16(1)
1.5.6 RF Bipolar Circuits ESD Failure Mechanisms
17(1)
1.6 RF Basics
17(4)
1.7 Two-Port Network Parameters
21(3)
1.7.1 Z-Parameters
21(1)
1.7.2 Y-Parameters
22(1)
1.7.3. S-Parameters
22(1)
1.7.4 T-Parameters
23(1)
1.8 Stability: RF Design Stability and ESD
24(2)
1.9 Device Degradation and ESD Failure
26(3)
1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria
26(2)
1.9.2 RF Parameters, ESD Degradation, and Failure Criteria
28(1)
1.10 RF ESD Testing
29(10)
1.10.1 ESD Testing Models
29(4)
1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology
33(4)
1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology
37(2)
1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing
39(7)
1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation
40(4)
1.11.2 ESD Degradation System Level Method – Eye Tests
44(2)
1.12 Product Level ESD Test and RF Functional Parameter Failure
46(2)
1.13 Combined RF and ESD TLP Test Systems
48(3)
1.14 Closing Comments and Summary
51(1)
Problems
52(1)
References
53(8)
Chapter 2 RF ESD Design 61(50)
2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows
61(3)
2.1.1 Ideal ESD Networks and the Current–Voltage d.c. Design Window
61(2)
2.1.2 Ideal ESD Networks in the Frequency Domain Design Window
63(1)
2.2 RF ESD Design Methods: Linearity
64(4)
2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit
68(2)
2.4 RF ESD Design Methods: Method of Substitution
70(3)
2.4.1 Method of Substitution of Passive Element to ESD Network Element
71(1)
2.4.2 Substitution of ESD Network Element to Passive Element
72(1)
2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks
73(6)
2.5.1 RF ESD Method – Conversion of Matching Networks to ESD Networks
74(2)
2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks
76(1)
2.5.2.1 Conversion of ESD Networks into L-Match Networks
76(1)
2.5.2.2 Conversion of ESD Networks into H-Match Networks
77(1)
2.5.2.3 Conversion of ESD Networks into T-Match Networks
78(1)
2.6 RF ESD Design Methods: Inductive Shunt
79(3)
2.7 RF ESD Design Methods: Cancellation Method
82(7)
2.7.1 Quality Factors and the Cancellation Method
82(1)
2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit
83(2)
2.7.3 Cancellation Method and ESD Circuitry
85(4)
2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator
89(2)
2.9 RF ESD Design Methods: Lumped versus Distributed Loads
91(4)
2.9.1 RF ESD Distributed Load with Coplanar Wave Guides
92(1)
2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices
93(2)
2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration
95(6)
2.10.1 ESD Power Clamp Placement Within a Domain
96(1)
2.10.2 Power Bus Architecture and ESD Design Synthesis
97(1)
2.10.3 VDT-to-Vss Power Rail Protection
98(1)
2.10.4 VDD-to-Analog VDD and VDD-to-RF Vic Power Rail Protection
99(1)
2.10.5 Interdomain ESD Protection Networks
100(1)
2.11 ESD Circuits and RF Bond Pad Integration
101(2)
2.12 ESD Structures Under Wire Bond Pads
103(3)
2.13 Summary and Closing Comments
106(1)
Problems
106(2)
References
108(3)
Chapter 3 RF CMOS and ESD 111(28)
3.1 RF CMOS: ESD Device Comparisons
111(5)
3.2 Circular RF ESD Devices
116(2)
3.3 RF ESD Design—ESD Wiring Design
118(2)
3.4 RF Passives: ESD and Schottky Barrier Diodes
120(2)
3.5 RF Passives: ESD and Inductors
122(5)
3.6 RF Passives: ESD and Capacitors
127(4)
3.6.1 Metal-oxide-Semiconductor and Metal–Insulator–Metal Capacitors
128(1)
3.6.2 Varactors and Hyper-Abrupt Junction Varactor Capacitors
128(1)
3.6.3 Metal-ILD-Metal Capacitors
129(1)
3.6.4 Vertical Parallel Plate (VPP) Capacitors
130(1)
3.7 Summary and Closing Comments
131(1)
Problems
132(1)
References
133(6)
Chapter 4 RF CMOS ESD Networks 139(44)
4.1 RF CMOS Input Circuits
139(6)
4.1.1 RF CMOS ESD Diode Networks
139(4)
4.1.2 RF CMOS Diode String ESD Network
143(2)
4.2 RF CMOS: Diode–Inductor ESD Networks
145(4)
4.2.1 RF Inductor–Diode ESD Networks
147(1)
4.2.2 RF Diode–Inductor ESD Networks
148(1)
4.3 RF CMOS Impedance Isolation LC Resonator ESD Networks
149(3)
4.3.1 RF CMOS LC–Diode ESD Networks
150(1)
4.3.2 RF CMOS Diode–LC ESD Networks
150(1)
4.3.3 Experimental Results of the RF CMOS LC–Diode Networks
151(1)
4.4 RF CMOS LNA ESD Design
152(5)
4.4.1 RF LNA ESD Design: Low Resistance ESD Inductor and ESD Diode Clamping Elements in H-Configuration
153(4)
4.5 RF CMOS T-Coil Inductor ESD Input Network
157(2)
4.6 RF CMOS Distributed ESD Networks
159(6)
4.6.1 RF CMOS Distributed RF ESD Networks
159(1)
4.6.2 RF CMOS Distributed RF ESD Networks using Series Inductor and Dual-Diode Shunt
160(3)
4.6.3 RF CMOS Distributed RF ESD Networks using Series Inductor and MOSFET Parallel Shunt
163(2)
4.7 RF CMOS Distributed ESD Networks: Transmission Lines and Coplanar Waveguides
165(2)
4.8 RF CMOS: ESD and RF LDMOS Power Technology
167(3)
4.9 RF CMOS ESD Power Clamps
170(6)
4.9.1 RC-Triggered MOSFET ESD Power Clamp
172(2)
4.9.2 High Voltage RC-Triggered MOSFET ESD Power Clamp
174(1)
4.9.3 Voltage-Triggered MOSFET ESD Power Clamps
175(1)
4.10 Summary and Closing Comments
176(1)
Problems
177(1)
References
178(5)
Chapter 5 Bipolar Physics 183(34)
5.1 Bipolar Device Physics
183(3)
5.1.1 Bipolar Transistor Current Equations
183(1)
5.1.2 Bipolar Current Gain and Collector-to-Emitter Transport
184(1)
5.1.3 Unity Current Gain Cutoff Frequency
185(1)
5.1.4 Unity Power Gain Cutoff Frequency
186(1)
5.2 Transistor Breakdown
186(4)
5.2.1 Avalanche Multiplication and Breakdown
186(2)
5.2.2 Bipolar Transistor Breakdown
188(2)
5.3 Kirk Effect
190(1)
5.4 Johnson Limit: Physical Limitations of the Transistor
191(4)
5.4.1 Voltage–Frequency Relationship
191(2)
5.4.2 Johnson Limit Current–Frequency Formulation
193(1)
5.4.3 Johnson Limit Power Formulation
194(1)
5.5 RF Instability: Emitter Collapse
195(6)
5.6 ESD RF Design Layout: Emitter, Base, and Collector Configurations
201(3)
5.7 ESD RF Design Layout: Utilization of a Second Emitter (Phantom Emitter)
204(4)
5.8 ESD RF Design Layout: Emitter Ballasting
208(2)
5.9 ESD RF Design Layout: Thermal Shunts and Thermal Lenses
210(1)
5.10 Base-Ballasting and RF Stability
211(2)
5.11 Summary and Closing Comments
213(1)
Problems
213(1)
References
214(3)
Chapter 6 Silicon Germanium and ESD 217(52)
6.1 Heterojunctions and Silicon Germanium Technology
217(4)
6.1.1 Silicon Germanium HBT Devices
218(1)
6.1.2 Silicon Germanium Device Structure
219(2)
6.2 Silicon Germanium Physics
221(3)
6.3 Silicon Germanium Carbon
224(2)
6.4 Silicon Germanium ESD Measurements
226(7)
6.4.1 Silicon Germanium Collector-to-Emitter ESD Stress
227(2)
6.4.2 ESD Comparison of Silicon Germanium HBT and Silicon BJT
229(3)
6.4.3 SiGe HBT Electrothermal Human Body Model (HBM) Simulation of Collector–Emitter Stress
232(1)
6.5 Silicon Germanium Carbon Collector–Emitter ESD Measurements
233(4)
6.6 Silicon Germanium Transistor Emitter–Base Design
237(22)
6.6.1 Epitaxial-Base Heterojunction Bipolar Transistor (HBT) Emitter–Base Design
238(2)
6.6.2 Emitter–Base Design RF Frequency Performance Metrics
240(1)
6.6.3 SiGe HBT Emitter–Base Resistance Model
240(1)
6.6.4 SiGe HBT Emitter–Base Design and Silicide Placement
241(4)
6.6.5 Self-Aligned (SA) Emitter–Base Design
245(3)
6.6.6 Non-self aligned (NSA) Emitter–Base Design
248(8)
6.6.6.1 NSA Human Body Model (HBM) Step Stress
249(1)
6.6.6.2 Transmission Line Pulse (TLP) Step Stress
250(1)
6.6.6.3 RF Testing of SiGe HBT Emitter–Base Configuration
251(3)
6.6.6.4 Unity Current Gain Cutoff Frequency–Collector Current Plots
254(2)
6.6.7 Silicon Germanium Carbon – ESD-Induced S-Parameter Degradation
256(2)
6.6.8 Electrothermal Simulation of Emitter–Base Stress
258(1)
6.7 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data
259(1)
6.8 Silicon Germanium HBT Multiple-Emitter Study
260(2)
6.9 Summary and Closing Comments
262(1)
Problems
262(1)
References
263(6)
Chapter 7 Gallium Arsenide and ESD 269(18)
7.1 Gallium Arsenide Technology and ESD
269(1)
7.2 Gallium Arsenide Energy-to-Failure and Power-to-Failure
269(3)
7.3 Gallium Arsenide ESD Failures in Active and Passive Elements
272(1)
7.4 Gallium Arsenide HBT Devices and ESD
273(4)
7.4.1 Gallium Arsenide HBT Device ESD Results
274(1)
7.4.2 Gallium Arsenide HBT Diode Strings
275(2)
7.5 Gallium Arsenide HBT-Based Passive Elements
277(2)
7.5.1 GaAs HBT Base–Collector Varactor
277(2)
7.6 Gallium Arsenide Technology Table of Failure Mechanisms
279(1)
7.7 Indium Gallium Arsenide and ESD
279(2)
7.8 Indium Phosphide (InP) and ESD
281(1)
7.9 Summary and Closing Comments
281(1)
Problems
281(1)
References
282(5)
Chapter 8 Bipolar Receiver Circuits and Bipolar ESD Networks 287(52)
8.1 Bipolar Receivers and ESD
287(1)
8.2 Single Ended Common-Emitter Receiver Circuits
288(12)
8.2.1 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors
289(1)
8.2.2 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors and ESD Protection
290(1)
8.2.3 Bipolar Single-Ended Common-Emitter Receiver Circuit with Feedback Circuit
291(2)
8.2.3.1 Bipolar Single-Ended Common-Emitter Circuit with Resistor Feedback Element
291(1)
8.2.3.2 Bipolar Single-Ended Common-Emitter Receiver Circuit with Resistor–Capacitor Feedback Element
292(1)
8.2.4 Bipolar Single-Ended Common-Emitter Receiver Circuit with Emitter Degeneration
293(4)
8.2.5 Bipolar Single-Ended Common Emitter Circuit with Balun Output
297(1)
8.2.6 Bipolar Single-Ended Series Cascode Receiver Circuits
298(2)
8.3 Bipolar Differential Receiver Circuits
300(3)
8.3.1 Bipolar Differential Cascode Common-Emitter Receiver Circuits
302(1)
8.4 Bipolar ESD Input Circuits
303(9)
8.4.1 Diode-Configured Bipolar ESD Input Circuits
307(1)
8.4.2 Bipolar ESD Input: Resistor Grounded Base Bipolar ESD Input
308(4)
8.5 Bipolar-Based ESD Power Clamps
312(22)
8.5.1 Bipolar Voltage-Triggered ESD Power Clamps
312(1)
8.5.2 Zener Breakdown Voltage-Triggered ESD Power Clamps
312(6)
8.5.3 BVcEo Voltage-Triggered ESD Power Clamps
318(5)
8.5.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO Breakdown Synthesized Bipolar ESD Power Clamps
323(5)
8.5.5 Ultra-Low Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamps
328(4)
8.5.6 Capacitively-Triggered BiCMOS ESD Power Clamps
332(2)
8.6 Bipolar ESD Diode String and Triple-Well Power Clamps
334(1)
8.7 Summary and Closing Comments
335(1)
Problems
335(2)
References
337(2)
Chapter 9 RF and ESD Computer-Aided Design (CAD) 339(36)
9.1 RF ESD Design Environment
339(2)
9.1.1 Electrostatic Discharge and Radio Frequency (RF) Cosynthesis Design Methods
339(1)
9.1.2 ESD Hierarchical Pcell Physical Layout Generation
340(1)
9.1.3 ESD Hierarchical Pcell Schematic Generation
341(1)
9.2 ESD Design with Hierarchical Parameterized Cells
341(6)
9.2.1 Hierarchical Pcell Graphical Method
342(2)
9.2.2 Hierarchical Pcell Schematic Method
344(3)
9.3 ESD Design of RF CMOS-Based Hierarchical Parameterized Cells
347(2)
9.4 RF BiCMOS ESD Hierarchical Parameterized Cell
349(10)
9.4.1 BiCMOS ESD Input Networks
350(3)
9.4.2 BiCMOS ESD Rail-to-Rail
353(1)
9.4.3 BiCMOS ESD Power Clamps
354(5)
9.5 Advantages and Limitations of the RF ESD Design System
359(3)
9.6 Guard Ring P-Cell Methodology
362(8)
9.6.1 Guard Rings for Internal and External Latchup Phenomena
362(1)
9.6.2 Guard Ring Theory
363(2)
9.6.3 Guard Ring Design
365(2)
9.6.4 Guard Ring Characterization
367(3)
9.7 Summary and Closing Comments
370(1)
Problems
370(1)
References
371(4)
Chapter 10 Alternative ESD Concepts: On-Chip and Off-Chip ESD Protection Solutions 375(16)
10.1 Spark Gaps
375(3)
10.2 Field Emission Devices
378(4)
10.2.1 Field Emission Device (FED) as ESD Protection
378(1)
10.2.2 Field Emission Device in Gallium Arsenide Technology
379(1)
10.2.3 Field Emission Device Electronic Blunting Effect
380(1)
10.2.4 Field Emission Device Multiemitter ESD Design
380(2)
10.2.5 Field Emission Device (FED) ESD Design Practices
382(1)
10.3 Off-Chip Protection and Off-Chip Transient Suppression Devices
382(4)
10.3.1 Off-Chip Transient Voltage Suppression (TVS) Devices
383(1)
10.3.2 Off-Chip Polymer Voltage Suppression (PVS) Devices
384(2)
10.4 Package-Level Mechanical ESD Solutions
386(1)
10.5 RF Proximity Communications Chip-to-Chip ESD Design Practices
387(1)
10.6 Summary and Closing Comments
388(1)
Problems
389(1)
References
389(2)
Index 391


Steven H. Voldman is the author of ESD: RF Technology and Circuits, published by Wiley.
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