This book is a compilation of comprehensive studies done on the properties of graphene and its synthesis methods suitable for VLSI interconnects applications.
Copper (Cu) has been used as an interconnection material in the semiconductor industry for years owing to its best balance of conductivity and performance. However, it is running out of steam as it is approaching its limits with respect to electrical performance and reliability. Graphene is a non-metal material, but it can help to improve electromigration (EM) performance of Cu because of its excellent properties. Combining graphene with Cu for very large-scale integration (VLSI) interconnects can be a viable solution. The incorporation of graphene into Cu allows the present Cu fabrication back-end process to remain unaltered, except for the small step of inserting graphene into Cu. Therefore, it has a great potential to revolutionize the VLSI integrated circuit (VLSI-IC) industry and appeal for further advancement of the semiconductor industry. This book is a compilation of comprehensive studies done on the properties of graphene and its synthesis methods suitable for applications of VLSI interconnects. It introduces the development of a new method to synthesize graphene, wherein it not only discusses the method to grow graphene over Cu but also allows the reader to know how to optimize graphene growth, using statistical design of experiments (DoE), on Cu interconnects in order to obtain good-quality and reliable interconnects. It provides a basic understanding of grapheneCu interaction mechanism and evaluates the electrical and EM performance of graphenated Cu interconnects.
| Preface |
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ix | |
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1 | (16) |
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1.1 Importance of Interconnections in VLSI |
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1 | (1) |
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1.2 Copper Is Running Out of Steam |
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2 | (2) |
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1.3 Graphene as a Solution |
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4 | (5) |
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1.4 Properties and Applications of Graphene |
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9 | (2) |
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11 | (6) |
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2 Graphene Synthesis Methods |
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17 | (10) |
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2.1 Overview of Existing Methods |
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17 | (3) |
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2.1.1 Mechanical Exfoliation |
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17 | (1) |
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2.1.2 Graphite Sonication |
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18 | (1) |
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2.1.3 Graphene Oxide Reduction |
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18 | (1) |
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19 | (1) |
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2.2 Drawbacks of Current Methods with Respect to Applications in VLSI Interconnect Fabrication |
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20 | (2) |
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22 | (5) |
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3 Novel and Improved Graphene Synthesis Method |
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27 | (38) |
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3.1 Exploration of Carbon Sources |
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27 | (1) |
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3.2 Amorphous Carbon as a Promising Candidate: A PVD-Based Synthesis |
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28 | (13) |
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3.2.1 Exploration of Different Placements of Carbon Source |
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28 | (1) |
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3.2.1.1 Sample preparation using PVD method |
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28 | (1) |
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3.2.1.2 Post-PVD annealing |
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29 | (3) |
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32 | (4) |
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3.2.2 In-Depth Analysis of Best Placement of Carbon Source for Graphene Synthesis |
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36 | (1) |
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3.2.2.1 Sample preparation using PVD method |
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36 | (1) |
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3.2.2.2 Post-PVD annealing and characterization |
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37 | (4) |
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3.3 Growth Mechanism of PVD-Based Graphene |
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41 | (19) |
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3.3.1 Effect of Amorphous Carbon Thickness |
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41 | (2) |
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3.3.2 Effect of Annealing Time |
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43 | (2) |
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3.3.3 Effect of Annealing Temperature |
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45 | (1) |
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3.3.4 Stress Analysis Using Finite Element Modeling |
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46 | (4) |
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3.3.5 Interpretation of Experimental Results with the Aid of FEM |
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50 | (10) |
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60 | (5) |
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4 Statistical Approach to Identify Key Growth Parameters of the Novel Graphene Growth PVD Processes |
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65 | (26) |
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4.1 Brief History and Need of DoE |
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66 | (1) |
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67 | (1) |
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68 | (2) |
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4.4 Illustration of DoE for the Novel PVD Graphene Synthesis |
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70 | (16) |
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4.4.1 Attribute-Response Factorial Design |
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70 | (5) |
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4.4.2 Full-Factorial DoE Analysis |
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75 | (9) |
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4.4.3 Filtered DoE Approach |
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84 | (2) |
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86 | (5) |
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5 Copper-Graphene Interconnect |
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91 | (22) |
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91 | (1) |
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5.2 Electrical and Thermal Characteristics of Graphenated Copper |
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92 | (7) |
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92 | (1) |
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5.2.2 Experimentation and Results |
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92 | (1) |
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5.2.2.1 Temperature distribution measurement |
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92 | (1) |
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5.2.2.2 Electrical resistivity measurement |
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93 | (3) |
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5.2.3 Atomic Level Finite Element EM Modeling |
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96 | (3) |
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5.3 Compatibility of Graphenated Interconnect to Current Integrated Circuit Back-End Processes |
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99 | (2) |
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5.4 Novel Copper--Graphene--Copper Interconnect and Its Potential Performance |
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101 | (2) |
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5.5 Mechanism of Electroless Cu Deposition on Graphenated Cu |
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103 | (4) |
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107 | (6) |
| Index |
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113 | |
Cher-Ming Tan is Director of the Center for Reliability Sciences and Technologies (CReST) and a professor at the Department of Electronic Engineering as well as the Institute of Radiation Research, College of Medicine, Chang Gung University, Taoyuan, Taiwan. He is an honorary chair professor at the Center of Reliability Engineering, Ming Chi University of Technology, New Taipei, Taiwan, and a researcher at the Department of Urology, Chang Gung Memorial Hospital, Taoyuan, Taiwan. He earned his PhD (1992) in Electrical Engineering from the University of Toronto, Ontario, Canada. He joined Nanyang Technological University, Singapore, as a faculty member in 1997 and Chang Gung University in 2014. His research interests include materials analysis, failure analysis, reliability of electronics devices, reliability of system, reliability statistics, modeling, and simulation. Udit Narula is a postdoctoral research fellow at CReST. He completed his BTech (2011) from Maharshi Dayanand University, Haryana, India, and MTech (2013) from Amity University, Noida, India. He earned his PhD (2018) from the Department of Electronic Engineering, Chang Gung University. His research interests include graphene-based ULSI interconnects, graphene synthesis methods, and component/system reliability analysis and statistics. Vivek Sangwan is a postdoctoral research fellow at CReST. He completed his BTech (2012) from Dr. A. P. J. Abdul Kalam Technical University, Lucknow, India, and MTech (2014) from Amity University. He earned his PhD (2019) from the Department of Electronic Engineering, Chang Gung University. His research interests include failure and reliability analysis of electronic devices, DoE, and design and simulation of 3D models.
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