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E-grāmata: Integrated Circuit Design for Radiation Environments

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  • Formāts: EPUB+DRM
  • Izdošanas datums: 03-Dec-2019
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9781118701850
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Integrated Circuit Design for Radiation EnvironmentsPalielināt
  • Formāts: EPUB+DRM
  • Izdošanas datums: 03-Dec-2019
  • Izdevniecība: John Wiley & Sons Inc
  • Valoda: eng
  • ISBN-13: 9781118701850
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A practical guide to the effects of radiation on semiconductor components of electronic systems, and techniques for the designing, laying out, and testing of hardened integrated circuits

This book teaches the fundamentals of radiation environments and their effects on electronic components, as well as how to design, lay out, and test cost-effective hardened semiconductor chips not only for today’s space systems but for commercial terrestrial applications as well. It provides a historical perspective, the fundamental science of radiation, and the basics of semiconductors, as well as radiation-induced failure mechanisms in semiconductor chips.

Integrated Circuits Design for Radiation Environments starts by introducing readers to semiconductors and radiation environments (including space, atmospheric, and terrestrial environments) followed by circuit design and layout. The book introduces radiation effects phenomena including single-event effects, total ionizing dose damage and displacement damage) and shows how technological solutions can address both phenomena.

  • Describes the fundamentals of radiation environments and their effects on electronic components
  • Teaches readers how to design, lay out and test cost-effective hardened semiconductor chips for space systems and commercial terrestrial applications
  • Covers natural and man-made radiation environments, space systems and commercial terrestrial applications
  • Provides up-to-date coverage of state-of-the-art of radiation hardening technology in one concise volume
  • Includes questions and answers for the reader to test their knowledge

Integrated Circuits Design for Radiation Environments will appeal to researchers and product developers in the semiconductor, space, and defense industries, as well as electronic engineers in the medical field. The book is also helpful for system, layout, process, device, reliability, applications, ESD, latchup and circuit design semiconductor engineers, along with anyone involved in micro-electronics used in harsh environments.

About the Authors xiii
Preface xix
Acknowledgments xxiii
Glossary of Terms xxv
1 Introduction and Historical Perspective 1(30)
1.1 Introduction
1(1)
1.2 Discovery of X-Rays, Radiation, and Subatomic Particles
2(6)
1.3 The Nuclear Age
8(1)
1.4 The Space Age
9(6)
1.5 Semiconductors - Revolution, Evolution, and Scaling
15(5)
1.6 Beginning of Ionizing Radiation Effects in Semiconductors
20(2)
1.7 Beginning of Single-Event Effects in Semiconductors
22(4)
1.8 Summary and Closing Comments
26(1)
References
27(4)
2 Radiation Environments 31(54)
2.1 Introduction
31(1)
2.2 X-Rays, Gamma Rays, and the Atom
31(24)
2.2.1 X-Rays
31(3)
2.2.2 X-Ray Absorption
34(2)
2.2.3 Auger Electrons
36(1)
2.2.4 Nuclear Structure and Binding Energy
36(14)
2.2.4.1 Models of the Nucleus
38(12)
2.2.5 Alpha and Beta Decay
50(3)
2.2.5.1 Alpha Decay
51(1)
2.2.5.2 Beta Decay
52(1)
2.2.6 Gamma-Ray Emission or Gamma Decay
53(1)
2.2.7 Other Types of Nuclear Radiation
54(1)
2.3 Natural Radioactivity
55(3)
2.3.1 Exponential Decay
55(1)
2.3.2 Decay Series
56(2)
2.4 The Space Environment
58(13)
2.4.1 Solar Radiation
59(3)
2.4.2 Trapped Radiation
62(4)
2.4.3 Cosmic Rays
66(3)
2.4.4 Atmospheric Neutrons
69(2)
2.5 The Nuclear Reactor Environment
71(4)
2.6 The Weapons Environment
75(3)
2.7 The Environment in High-Energy Physics Facilities
78(2)
2.8 Summary and Closing Comments
80(1)
References
81(4)
3 Radiation Effects in Semiconductor Materials 85(58)
3.1 Introduction
85(1)
3.2 Basic Effects
86(25)
3.2.1 Heavy Charged Particles
86(7)
3.2.1.1 Stopping Power
86(1)
3.2.1.2 Electronic Stopping
87(5)
3.2.1.3 Nuclear Stopping
92(1)
3.2.2 Electrons
93(8)
3.2.2.1 Electromagnetic Radiation
93(3)
3.2.2.2 Stopping Power
96(5)
3.2.3 Neutrons
101(5)
3.2.3.1 Neutron Cross Section
102(1)
3.2.3.2 Interactions with Matter
103(3)
3.2.4 Photons (X-Rays, Gamma Rays)
106(5)
3.2.4.1 Photoelectric Effect
107(1)
3.2.4.2 Compton Scattering
108(1)
3.2.4.3 Pair Production
109(1)
3.2.4.4 Photonuclear Reactions
110(1)
3.3 Charge Trapping in Silicon Dioxide
111(20)
3.3.1 Charge Generation/Recombination
111(7)
3.3.1.1 Geminate and Columnar Models
112(1)
3.3.1.2 Geminate Recombination
113(2)
3.3.1.3 Columnar Recombination
115(2)
3.3.1.4 Numerical Methods
117(1)
3.3.2 Hole Trapping and Transport
118(6)
3.3.2.1 E' Centers
120(2)
3.3.2.2 Continuous-Time Random-Walk (CTRW)
122(2)
3.3.3 The Silicon/Silicon Dioxide Interface
124(19)
3.3.3.1 Interface Traps
125(2)
3.3.3.2 Border Traps
127(1)
3.3.3.3 Hydrogen
128(2)
3.3.3.4 ELDRS
130(1)
3.4 Bulk Damage
131(2)
3.5 Summary and Closing Comments
133(2)
References
135(8)
4 Radiation-Induced Single Events 143(30)
4.1 Introduction - Single-Events Effects (SEE)
143(5)
4.1.1 Single-Event Upsets (SEU)
143(1)
4.1.2 Multiple-Bit Upset (MBU)
143(1)
4.1.3 Single-Event Transients (SET)
144(1)
4.1.4 Single-Event Functional Interrupts (SEFIs)
144(1)
4.1.5 Single-Event Disturb (SED)
145(1)
4.1.6 Single-Event Snapback (SESB)
146(1)
4.1.7 Single-Event Latchup (SEL)
146(1)
4.1.8 Single-Event Burnout (SEB)
146(1)
4.1.9 Single-Event Gate Rupture (SEGR)
147(1)
4.1.10 Single-Event Hard Errors (SHE)
147(1)
4.2 Single-Event Upset (SEU)
148(1)
4.2.1 SEU - Memory
148(1)
4.2.2 SEU in CMOS Memory
148(1)
4.2.3 SEU in Bipolar Memory
148(1)
4.2.4 SEU in CMOS SRAM
149(1)
4.2.5 SEU in Future Technology - FINFETs
149(1)
4.3 SEU - Particle Sources
149(5)
4.3.1 SEU Source - Alpha Particles
150(2)
4.3.2 SEU Source - Pions and Muons
152(1)
4.3.3 SEU - Neutrons
153(1)
4.3.4 SEU Source - Protons
153(1)
4.3.5 SEU - Heavy Ions
154(1)
4.4 Single-Event Gate Rupture (SEGR)
154(4)
4.4.1 Definition SEGR
155(1)
4.4.2 SEGR Source - Ion Track
155(1)
4.4.3 SEGR Source - Failure Mechanism
156(1)
4.4.4 SEGR - Modeling and Simulation
156(1)
4.4.5 Power Transistors and SEGR
156(2)
4.4.5.1 Lateral Power Transistors SEGR
156(1)
4.4.5.2 Vertical MOS (VMOS) SEGR
157(1)
4.4.5.3 Advanced Technologies - Planar MOSFET SEGR
157(1)
4.5 Single-Event Transients (SETS)
158(1)
4.5.1 SET Definition
158(1)
4.5.2 SET Source
158(1)
4.5.3 SET Source Failure Mechanisms
159(1)
4.5.4 SET in Integrated Circuits
159(1)
4.5.4.1 Digital Circuitry
159(1)
4.5.4.2 Continuous Time Analog Circuitry
159(1)
4.5.5 Prediction and Hardening
159(1)
4.6 Single-Event Latchup (SEL)
159(6)
4.6.1 SEL Definition
160(1)
4.6.2 SEL Source
160(1)
4.6.3 SEL Time Response
161(1)
4.6.4 SEL Maximum Charge Collection Evaluation in a Parallelepiped Region
162(2)
4.6.5 A SEL Design Practice
164(1)
4.6.6 SEL Semiconductor Device Simulation
165(1)
4.7 Summary and Closing Comments
165(1)
References
166(7)
5 Radiation Testing 173(36)
5.1 Introduction
173(2)
5.1.1 Radiation Units and Measurements
173(2)
5.2 Radiation Testing and Sources
175(26)
5.2.1 Total Ionizing Dose (TID) Testing
176(3)
5.2.2 Total Ionizing Dose (TID) Sources
179(3)
5.2.3 Single-Event Effects (SEE) Testing
182(5)
5.2.4 Single-Event Effects (SEE) Sources and Facilities
187(5)
5.2.5 Neutron Testing
192(1)
5.2.6 Neutron Sources
193(2)
5.2.7 Proton Testing
195(1)
5.2.8 Proton Sources
196(1)
5.2.9 Transient Gamma Testing
197(1)
5.2.10 Transient Gamma Sources
198(3)
5.3 Summary and Closing Comments
201(3)
References
204(5)
6 Device Modeling and Simulation Techniques 209(40)
6.1 Introduction
209(1)
6.2 Device Modeling
210(5)
6.2.1 Circuit Simulators
211(1)
6.2.2 Intrinsic Models
212(1)
6.2.3 Composite Models and Inline Subcircuits
212(2)
6.2.4 Analysis and Statistics Programs
214(1)
6.3 Radiation Effects on Semiconductor Devices
215(21)
6.3.1 MOS Capacitors and Transistors
215(9)
6.3.1.1 MOS Capacitors
216(3)
6.3.1.2 MOS Transistors
219(5)
6.3.2 Diodes and Bipolar Transistors
224(6)
6.3.2.1 Diodes
224(1)
6.3.2.2 Bipolar Transistors
225(5)
6.3.3 Power Devices
230(2)
6.3.3.1 DMOS Composite Models
231(1)
6.3.3.2 Operating Voltage
232(1)
6.3.4 Other Devices
232(3)
6.3.4.1 Junction Field Effect Transistors (JFETs)
232(2)
6.3.4.2 Resistors
234(1)
6.3.4.3 Capacitors
235(1)
6.3.5 Some Modeling Challenges
235(1)
6.4 Circuit Simulation
236(6)
6.4.1 Corner Simulation
236(3)
6.4.2 SEE Simulation
239(3)
6.5 Summary and Closing Comments
242(2)
References
244(5)
7 Radiation Semiconductor Process and Layout Solutions 249(44)
7.1 Introduction
249(1)
7.2 Substrate Hardened Technologies
249(4)
7.2.1 Silicon-on-Insulator (SOI) Technologies
250(1)
7.2.1.1 Separation by Implanted Oxygen (SIMOX)
250(1)
7.2.1.2 Silicon-Bonded (SIBOND) Technology
250(1)
7.2.2 Silicon on Sapphire (SOS)
251(1)
7.2.3 Silicon on Diamond (SOD)
252(1)
7.2.4 Silicon on Nothing (SON)
252(1)
7.3 Oxide Hardening Technologies
253(2)
7.3.1 Oxide Growth and Fluorination of Oxide
253(1)
7.3.2 MOSFET Gate Oxide Hardening
253(1)
7.3.3 Recessed Oxide (ROX) Hardening
254(1)
7.3.4 LOCOS Isolation Hardening
254(1)
7.3.5 Shallow Trench Isolation (STI) Hardening
254(1)
7.4 CMOS Latchup Process Solutions
255(1)
7.5 CMOS Substrates - High-Resistance Substrates
255(5)
7.5.1 50 S2-cm Substrate Resistance
259(1)
7.6 Wells
260(4)
7.6.1 Single Well - Diffused N-Well
261(1)
7.6.2 Single Well - Retrograde N-Well
261(1)
7.6.3 Dual-Well Technology
262(2)
7.6.3.1 P-well and P++ Substrate
262(1)
7.6.3.2 P-Well and P+ Connecting Implant
263(1)
7.7 Triple-Well Technology
264(2)
7.7.1 Triple Well - Full Separation of Wells
264(1)
7.7.2 Triple Well - Merged Triple Well
265(1)
7.7.3 Triple Well - Merged Triple Well with Blanket Implant
266(1)
7.8 Sub-Collectors
266(2)
7.8.1 Epitaxial Grown Sub-Collector
266(1)
7.8.2 Implanted Sub-Collector
267(1)
7.8.3 Sub-Collector - NPN and PNP Bipolar Current Gain
267(1)
7.8.4 Sub-Collector - Beta Product βPNPβNPN
267(1)
7.9 Heavily Doped Buried Layers (HDBL)
268(2)
7.9.1 Buried Implanted Layer for Lateral Isolation (BILLI) Process
268(1)
7.9.2 Continuous HDBL Implant
268(2)
7.9.3 Buried Guard Ring (BGR)
270(1)
7.10 Isolation Concepts
270(7)
7.10.1 LOCOS Isolation
270(1)
7.10.2 Shallow Trench Isolation (STI)
270(1)
7.10.3 Dual Depth Isolation
271(1)
7.10.4 Trench Isolation (TI)
272(5)
7.10.4.1 Trench Isolation (TI) and Sub-Collector
274(3)
7.11 Deep Trench
277(7)
7.11.1 Deep Trench (DT) within PNPN Structure
279(2)
7.11.2 Deep Trench Structure and Sub-Collector
281(2)
7.11.3 Deep Trench Structure and Merged Triple Well
283(1)
7.12 Layout Solutions
284(2)
7.12.1 Polysilicon Bound Structures
284(1)
7.12.2 Parasitic Isolation Device (PID)
284(2)
7.13 Summary and Closing Comments
286(1)
References
287(6)
8 Single-Event Upset Circuit Solutions 293(12)
8.1 Introduction
293(1)
8.2 CMOS DRAM SEU Circuit Solutions
293(3)
8.2.1 CMOS DRAM Redundancy
294(1)
8.2.2 CMOS DRAM with SRAM Error Correction
294(2)
8.3 CMOS SRAM SEU Circuit Solution
296(3)
8.3.1 CMOS SRAM Four-Device Cell
296(1)
8.3.2 CMOS SRAM Six-Device Cell
297(1)
8.3.3 CMOS SRAM 12-Device Cell
298(1)
8.4 Bipolar SRAM
299(2)
8.4.1 Bipolar SRAM Cell with Resistor Loads
300(1)
8.4.2 Bipolar SRAM Cell with Resistor Loads and Schottky Clamps
300(1)
8.4.3 Bipolar SRAM Cell with PNP Transistors
301(1)
8.5 Bipolar SRAM Circuit Solutions
301(1)
8.6 SEU in CMOS Logic Circuitry
302(1)
8.7 Summary and Closing Comments
302(1)
References
303(2)
9 Latchup Circuit Solutions 305(28)
9.1 Introduction
305(1)
9.2 Power Supply Concepts
305(6)
9.2.1 Power Supply Current Limit - Series Resistor
305(1)
9.2.2 Power Supply Current Limit - Current Source
306(1)
9.2.3 Power Supply Solutions - Voltage Regulator
307(1)
9.2.4 Latchup Circuit Solutions - Power Supply Decoupling
308(3)
9.3 Overshoot and Undershoot Clamp Networks
311(7)
9.3.1 Passive Clamp Networks
312(1)
9.3.2 Active Clamp Networks
313(3)
9.3.3 Dynamic Threshold Triple Well Passive and Active Clamp Networks
316(2)
9.4 Passive and Active Guard Rings
318(8)
9.4.1 Passive Guard Ring Circuits and Structures
318(1)
9.4.2 Active Guard Ring Circuits and Structures
319(7)
9.5 Triple-Well Noise and Latchup Suppression Structures
326(1)
9.6 System-Level Latchup Issues
326(1)
9.7 Summary and Closing Comments
327(2)
References
329(4)
10 Emerging Effects and Future Technology 333(14)
10.1 Introduction
333(1)
10.2 Radiation Effects in Advanced Technologies
333(3)
10.2.1 Moore's Law, Scaling, and Radiation Effects
334(1)
10.2.2 Technology Lifetime and Reliability
334(1)
10.2.2.1 New Missions
335(1)
10.2.2.2 Throwaway Mentality
335(1)
10.2.2.3 New Space Entrants
335(1)
10.2.3 Terrestrial Issues
335(1)
10.2.4 Space Mission Issues
335(1)
10.2.5 Server Farms
335(1)
10.2.6 Automotive
336(1)
10.2.7 Internet of Things (IoT)
336(1)
10.2.8 More than Moore
336(1)
10.3 Radiation Effects in Semiconductor Nanostructures
336(4)
10.3.1 Planar MOSFETs in Sub-25 nm
337(1)
10.3.2 Bulk FinFET
338(1)
10.3.3 SOI FinFET
339(1)
10.3.4 3-D Circuits
340(1)
10.4 Radiation Effects and Advanced Packaging
340(2)
10.4.1 Radiation Effects and 2.5-D Circuits and Technology
341(1)
10.4.2 Radiation Effects and 3-D Circuits and Technology
341(1)
10.4.3 More than Moore and 3-D Integration
342(1)
10.5 Ruggedized Capability
342(1)
10.5.1 Ruggedized Capability for Radiation
343(1)
10.5.2 Ruggedized Capability for High Temperature
343(1)
10.6 Radiation Models
343(1)
10.7 A Nuclear World
344(1)
10.8 Summary and Closing Comments
344(1)
References
345(2)
Index 347
STEPHEN J. GAUL is a Senior Principal Engineer at Renesas Electronics Americas, Inc., Florida, USA. He has worked in the semiconductor/integrated circuit field for over 35 years and has authored many papers and over 35 patents, many specific to radiation-hard/radiation-tolerant techniques.

NICOLAAS VAN VONNO is currently a Principal Engineer at Renesas Electronics Americas, Inc., Florida, USA, and has been an independent consultant in the radiation effects field. He has been Guest Editor, Session Chairman, and Short Course Chairman for the IEEE Nuclear and Space Radiation Effects Conference (NSREC).

STEVEN H. VOLDMAN, Ph.D., is a Consultant on ESD and latchup, as well as invention and patenting. He is a Fellow of the Electrical and Electronics Engineers (IEEE) and author of over 10 books and 262 patents.

WESLEY H. MORRIS is President of Silicon-X (Technology focus), hardening CMOS devices to radiation and extreme temperatures. His career experience includes development of RH CMOS devices with SOS (RCA) and SOI (Harris), the first to prove bulk CMOS devices can be made latchup immune to extreme SEE radiation and operate reliably at high temperatures (250C). Morris is an author/inventor with multiple papers and patents related to RH and HT topics.
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