This book describes the need of copyright protection for multimedia objects and develops an invisible image watermarking scheme to serve the purpose of copyright protection. Here intelligent systems are introduced to generate a better visual transparency with increased payload.
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xi | |
| Acknowledgments |
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xv | |
| About the Authors |
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xvii | |
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1 | (26) |
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1.1 Information Hiding and Copyright Protection |
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1 | (10) |
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1 | (1) |
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2 | (1) |
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3 | (3) |
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6 | (5) |
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1.2 Digital Watermarking as a Copyright Protection Tool |
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11 | (16) |
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11 | (2) |
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13 | (3) |
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16 | (3) |
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1.2.4 Properties for a Good Digital Watermarking Scheme |
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19 | (2) |
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21 | (3) |
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24 | (3) |
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Chapter 2 Perspectives on Digital Image Watermarking |
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27 | (32) |
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2.1 Introduction to Digital Image |
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27 | (5) |
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2.2 Various Techniques of Digital Image Watermarking |
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32 | (12) |
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2.2.1 Spatial Domain Practices |
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32 | (3) |
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2.2.2 Frequency Domain Practices |
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35 | (9) |
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2.3 Some Existing Frameworks for Digital Image Watermarking |
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44 | (15) |
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Chapter 3 Intelligent Systems Used in Copyright Protection |
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59 | (16) |
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3.1 Visual Saliency and its Purpose in Digital Watermarking |
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61 | (6) |
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3.1.1 Saliency and Salient Object |
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61 | (1) |
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3.1.2 The Purpose of Saliency in Digital Watermarking |
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61 | (1) |
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3.1.3 Saliency Detection and a Saliency Map |
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62 | (2) |
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3.1.4 Various Saliency Map Algorithms for Images |
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64 | (3) |
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3.2 Intelligent Image Clustering: The K-Means Algorithm |
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67 | (8) |
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67 | (3) |
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3.2.2 Need for Data Clustering in Digital Image Watermarking |
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70 | (1) |
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3.2.3 K-means Algorithm for Data Clustering |
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71 | (4) |
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Chapter 4 Copyright Protection Framework |
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75 | (16) |
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4.1 Watermark Embedding System |
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75 | (11) |
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Step 1 Evaluating the Saliency Map from the Cover Image |
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77 | (3) |
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Step 2 Constructing the Hiding Capacity Map from the Saliency Map |
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80 | (3) |
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Step 3 Constituting the Watermarked Image through Adaptive LSB Replacement |
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83 | (3) |
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4.2 Watermark Extracting System |
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86 | (5) |
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Chapter 5 Hardware Implementation |
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91 | (14) |
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5.1 Overview of Hardware Realization for Digital Watermarking |
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92 | (4) |
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5.2 Hardware Architecture for the Proposed Image Watermarking Scheme |
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96 | (9) |
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5.2.1 Watermark Embedding System |
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96 | (4) |
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5.2.2 Watermark Extracting System |
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100 | (5) |
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Chapter 6 System Evaluation |
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105 | (26) |
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6.1 Embedding System Outcomes |
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105 | (3) |
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6.2 Estimation of Data Hiding Capacity |
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108 | (1) |
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6.3 Analysis of Imperceptibility or Data Transparency |
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109 | (13) |
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6.3.1 Description of Image Quality Metrics, Involved in Imperceptibility Analysis |
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109 | (6) |
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6.3.2 Evaluation of Imperceptibility for the Proposed Watermarking Scheme |
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115 | (7) |
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6.4 Outputs of the Watermark Extracting System and its Efficacy in Terms of Robustness |
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122 | (3) |
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6.5 Comparative Study on the Proficiency of the Proposed Watermarking System |
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125 | (1) |
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6.6 An Evaluation of Hardware Systems for the Proposed Watermarking Logic |
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126 | (5) |
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131 | (4) |
| References |
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135 | (16) |
| Index |
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151 | |
Mr. Subhrajit Sinha Roy received his B. Tech. in Electronics and Communication Engineering from West Bengal University of Technology in 2012 and M. Tech. in Telecommunication from RCC Institute of Information Technology (under West Bengal University of Technology), Kolkata, India, in 2015. At present he is an Assistant Professor in the department of Electronics and Communication Engineering at Global Institute of Management and Technology, Krishnagar, West Bengal, India. He has also been enrolled in the Department of Radio Physics and Electronics under Calcutta University for Ph.D in Engineering and Technology. Till date he has six research publications in international journals, conference proceedings and edited volumes to his credit. His field of interest spans digital image processing, information hiding, FPGA based system design, low power VLSI design and quantum computing.
Dr. Abhishek Basu received his B. Tech. in Electronics and Telecommunication Engineering from West Bengal University of Technology in the year 2005, M. Tech. in VLSI Design from Institute of Radio Physics and Electronics, University of Calcutta, India in 2008 and Ph. D (Engg) from Jadavpur University, India in 2015. He is currently the Assistant Professor and Head of the Department of Electronics and Communication Engineering department of RCC Institute of Information Technology, Kolkata, India. He served as under graduate Program coordinator in the above mentioned Dept. during 30th march 2016 to 1st January, 2017. He is co-editor of a book and has more than 40 research publications in international journals, conference proceedings and edited volumes to his credit. He is the hospitality chair of International Conference on Intelligent Control, Power and Instrumentation (ICICPI 2016), during October 21th -23th, 2016. He is the member of the organizing and technical program committees of several national and international conferences. His research interests include digital image processing, visual information hiding, IP protection technique, FPGA based system design, low power VLSI Design and embedded system design. Dr. Basu is a life member of Indian Association for Productivity, Quality and Reliability, India.
Dr. Avik Chattopadhyay received his B. Tech. in Electronics and Telecommunication Engineering from West Bengal University of Technology in the year 2006, M. Tech. (in VLSI Design) and Ph. D. (Tech.) from the Institute of Radio Physics and Electronics, University of Calcutta, India in 2009 and 2013, respectively. He is currently an Assistant Professor with the Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, India. Prior to this, he served as Assistant Professor of Electrical and Electronics Engineering department of Birla Institute of Technology and Science, Pilani, Rajasthan, India almost for two years. He is co-author of a book-chapter and has more than 20 research publications in international journals, and conference proceedings to his credit. His research interests include design and analysis of novel structures of MOSFETs, study of post-CMOS devices for low power VLSI applications, and designing of FPGA based system.
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