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Microfluidic Very Large Scale Integration (VLSI): Modeling, Simulation, Testing, Compilation and Physical Synthesis 1st ed. 2016 [Hardback]

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  • Formāts: Hardback, 270 pages, height x width: 235x155 mm, weight: 5561 g, 101 Illustrations, color; 47 Illustrations, black and white; XV, 270 p. 148 illus., 101 illus. in color., 1 Hardback
  • Izdošanas datums: 16-Feb-2016
  • Izdevniecība: Springer International Publishing AG
  • ISBN-10: 3319295977
  • ISBN-13: 9783319295978
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Microfluidic Very Large Scale Integration (VLSI): Modeling, Simulation, Testing, Compilation and Physical Synthesis 1st ed. 2016Palielināt
  • Formāts: Hardback, 270 pages, height x width: 235x155 mm, weight: 5561 g, 101 Illustrations, color; 47 Illustrations, black and white; XV, 270 p. 148 illus., 101 illus. in color., 1 Hardback
  • Izdošanas datums: 16-Feb-2016
  • Izdevniecība: Springer International Publishing AG
  • ISBN-10: 3319295977
  • ISBN-13: 9783319295978
Citas grāmatas par šo tēmu:
Permanent link: https://www.kriso.lv/db/9783319295978.html
Keywords:
This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market.

Introduction.- Part 1. Preliminaries.- Design Methodologyfor Flow-based Microfluidic Biochips.- Biochip Architecture Model.- BiochemicalApplication Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- ApplicationMapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3.Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-ChipControl Synthesis.- Testing and Fault-Tolerant Design.
1 Introduction
1(14)
1.1 Microfluidic Biochips
1(2)
1.2 mVLSI Technology
3(5)
1.2.1 Application Areas
4(2)
1.2.2 Motivation for Automated Physical Design and Testing Techniques
6(2)
1.2.3 Motivation for Programming and Control of mVLSI Biochips
8(1)
1.3 Overview
8(7)
References
10(5)
Part I Preliminaries
2 Design Methodology for Flow-Based Microfluidic Biochips
15(14)
2.1 Modeling and Simulation
17(3)
2.2 Physical Design and Testing
20(3)
2.3 Programming and Control
23(6)
References
25(4)
3 Biochip Architecture Model
29(24)
3.1 Microfluidic Valve
29(2)
3.2 Component Design
31(2)
3.2.1 Pneumatic Switches
31(1)
3.2.2 Pneumatic Mixer
31(2)
3.3 Illustrative Example
33(2)
3.4 Component Model and Library
35(1)
3.4.1 Component Model
35(1)
3.4.2 Component Model Library
36(1)
3.5 System-Level Architecture Model
36(4)
3.6 On-Chip Control
40(13)
3.6.1 Pneumatic Logical Components
44(4)
3.6.2 Supportive Components
48(2)
3.6.3 Logical Circuits
50(1)
3.6.4 Logic Truth Tables
51(1)
References
51(2)
4 Biochemical Application Modeling
53(14)
4.1 High-Level Protocol Language: Aqua
53(4)
4.1.1 Declarations
54(2)
4.1.2 Statements
56(1)
4.2 Biochemical Application Model
57(2)
4.3 Benchmarks
59(8)
4.3.1 Real-Life Benchmarks
60(2)
4.3.2 Synthetic Benchmarks
62(2)
References
64(3)
Part II Compilation
5 Compiling High-Level Languages
67(26)
5.1 Problem Formulation
67(1)
5.2 Application Model Synthesis
68(12)
5.2.1 High-Level Language Grammar
70(3)
5.2.2 Generating the Application Graph
73(7)
5.3 Solving the Mixing Problem
80(13)
References
91(2)
6 Application Mapping and Simulation
93(18)
6.1 Application Mapping
94(2)
6.1.1 Problem Formulation
96(1)
6.2 Constraint Programming Strategy
96(3)
6.2.1 Finite Domain Variables
97(1)
6.2.2 Resource Binding Constraints
98(1)
6.2.3 Resource Sharing Constraints
98(1)
6.2.4 Precedence Constraints
99(1)
6.2.5 Cost Function
99(1)
6.3 List Scheduling Strategy
99(4)
6.3.1 Route Generation
102(1)
6.3.2 Optimization
103(1)
6.4 Experimental Evaluation
103(3)
6.5 Simulation
106(5)
References
109(2)
7 Control Synthesis and Pin-Count Minimization
111(16)
7.1 Biochip Control Synthesis
113(6)
7.1.1 Control Logic Generation
116(1)
7.1.2 Pin-Count Minimization
117(2)
7.1.3 Problem Formulation
119(1)
7.2 Synthesis Strategy
119(3)
7.2.1 Control Logic Generation
119(1)
7.2.2 Pin-Count Minimization
120(2)
7.3 Experimental Evaluation
122(5)
References
124(3)
Part III Physical Design
8 Allocation and Schematic Design
127(18)
8.1 Problem Formulation
128(1)
8.2 Allocation and Schematic Design
129(2)
8.2.1 Allocation and Schematic Design
129(2)
8.3 Synthesis Strategy
131(5)
8.3.1 Allocation
131(3)
8.3.2 Schematic Design
134(2)
8.4 Experimental Evaluation
136(9)
References
144(1)
9 Placement and Routing
145(38)
9.1 Models, Component Library, and Design Rules
146(5)
9.1.1 Connection Model
148(1)
9.1.2 Grid Graph Model
148(2)
9.1.3 Route Model
150(1)
9.2 Problem Formulation
151(1)
9.2.1 Formalization
152(1)
9.3 Simulated Annealing
152(5)
9.3.1 Concept
152(1)
9.3.2 Implementation
153(4)
9.4 Approximated Cost Function
157(5)
9.4.1 Metrics
158(2)
9.4.2 Computing the Cost Function
160(2)
9.5 Routed Cost Function
162(13)
9.5.1 Routing Algorithms
162(4)
9.5.2 Metrics
166(3)
9.5.3 Computing the Cost Function
169(6)
9.6 Experimental Evaluation
175(8)
9.6.1 Benchmarks
176(1)
9.6.2 Placement Quality
176(4)
9.6.3 Performance
180(2)
References
182(1)
10 On-Chip Control Synthesis
183(58)
10.1 Circuit Design
185(19)
10.1.1 Ongoing Example
186(1)
10.1.2 Two-Level Minimization
187(6)
10.1.3 Multiple-Level Optimization
193(4)
10.1.4 Library Binding
197(7)
10.2 Control Synthesis
204(5)
10.2.1 Component Control Logic Generation
204(2)
10.2.2 Routing Control Logic Generation
206(3)
10.3 Physical Synthesis
209(18)
10.3.1 Placement
211(4)
10.3.2 Routing
215(12)
10.4 Evaluation
227(1)
10.5 Benchmarks
228(5)
10.5.1 Evaluation of the Circuit Design
229(2)
10.5.2 Evaluation of the Placement Step
231(1)
10.5.3 Evaluation of the Routing Step
232(1)
10.6 On-Chip and Off-Chip Trade-Off
233(5)
10.7 On-Chip Control Circuits
238(3)
References
238(3)
11 Testing and Fault-Tolerant Design
241(28)
11.1 Fault Model and Testing
242(21)
11.1.1 Fault Model
242(4)
11.1.2 Testing
246(1)
11.1.3 Fault-Tolerant Architecture Synthesis
246(4)
11.1.4 Design Transformations
250(1)
11.1.5 Simulated Annealing
251(3)
11.1.6 GRASP
254(4)
11.1.7 Architecture Evaluation
258(5)
11.2 Experimental Evaluation
263(6)
References
267(2)
Index 269
Paul Pop is a professor at DTU Compute, Technical University of Denmark (DTU). He has received his Ph.D. degree in computer systems from Linkoping University in 2003. His main research interests are in the area of system-level design of embedded systems. He has published extensively in this area, and has received the best paper award at the DATE 2005, RTiS 2007, CASES 2009 and MECO 2013 conferences and the EDAA Outstanding Dissertations Award (co-supervisor) in 2011. Since 2008 he has also addressed Computer-Aided Design methods for biochips. His work in this area has received the best paper award at the CASES 2009 conference. He has co-organized and participated in tutorials and special sessions on CAD for biochips at conferences such as SOCC 2011, ESWEEK 2011, EMBC 2015 and ETS 2015.