Contributors |
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xi | |
Preface |
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xiii | |
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I Transceiver Concepts and Design |
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1 | (186) |
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1 Software-Defined Radio Front Ends |
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3 | (30) |
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3 | (1) |
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1.2 System-Level Considerations |
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4 | (1) |
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1.3 Wideband LO Synthesis |
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5 | (7) |
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1.4 Receiver Building Blocks |
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12 | (11) |
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1.5 Transmitter Building Blocks |
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23 | (2) |
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1.6 Calibration Techniques |
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25 | (2) |
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1.7 Full SDR Implementation |
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27 | (3) |
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30 | (3) |
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30 | (3) |
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2 Software-Defined Transceivers |
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33 | (32) |
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33 | (1) |
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34 | (1) |
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34 | (20) |
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2.4 Example of an SDR Transceiver |
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54 | (11) |
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60 | (5) |
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3 Adaptive Multi-Mode RF Front-End Circuits |
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65 | (20) |
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65 | (1) |
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3.2 Adaptive Multi-Mode Low-Power Wireless RF IC Design |
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66 | (2) |
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3.3 Multi-Mode Receiver Concept |
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68 | (2) |
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3.4 Design of a Multi-Mode Adaptive RF Front End |
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70 | (6) |
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3.5 Experimental Results for the Image-Reject Down-Converter |
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76 | (4) |
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80 | (5) |
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81 | (4) |
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4 Precise Delay Alignment Between Amplitude and Phase/Frequency Modulation Paths in a Digital Polar Transmitter |
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85 | (28) |
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85 | (2) |
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4.2 RF Polar Transmitter in Nanoscale CMOS |
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87 | (3) |
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4.3 Amplitude and Phase Modulation |
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90 | (6) |
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4.4 Mechanisms to Achieve Subnanosecond Amplitude and Phase Modulation Path Alignments |
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96 | (5) |
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4.5 Precise Alignment of Multi-Rate Direct and Reference Point Data |
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101 | (12) |
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109 | (4) |
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5 Overview of Front-End RF Passive Integration into SoCs |
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113 | (46) |
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113 | (6) |
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5.2 The Concept of a Receiver Translational Loop |
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119 | (3) |
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5.3 Feedforward Loop Nonideal Effects |
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122 | (3) |
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5.4 Feedforward Receiver Circuit Implementations |
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125 | (4) |
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5.5 Feedforward Receiver Experimental Results |
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129 | (4) |
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5.6 Feedback Notch Filtering for a WCDMA Transmitter |
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133 | (5) |
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5.7 Feedback-Based Transmitter Stability Analysis |
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138 | (3) |
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5.8 Impacts of Nonidealities in Feedback-Based Transmission |
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141 | (7) |
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5.9 Transmitter Building Blocks |
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148 | (2) |
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5.10 Feedback-Based Transmitter Measurement Results |
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150 | (3) |
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5.11 Conclusions and Discussion |
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153 | (6) |
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155 | (1) |
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156 | (3) |
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6 ADCs and DACs for Software-Defined Radio |
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159 | (28) |
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159 | (1) |
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6.2 ADC and DAC Requirements in Wireless Systems |
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160 | (2) |
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6.3 Multi-Standard Transceiver Architectures |
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162 | (3) |
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6.4 Evaluating Reconfigurability |
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165 | (1) |
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6.5 ADCs for Software-Defined Radio |
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166 | (6) |
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6.6 DACs for Software-Defined Radio |
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172 | (12) |
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184 | (3) |
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184 | (3) |
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187 | (160) |
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7 OFDM Transform-Domain Receivers for Multi-Standard Communications |
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189 | (30) |
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189 | (1) |
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7.2 Transform-Domain Receiver Background |
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190 | (1) |
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7.3 Transform-Domain Sampling Receiver |
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191 | (4) |
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7.4 Digital Baseband Design for the TD Receiver |
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195 | (9) |
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204 | (4) |
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208 | (3) |
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7.7 Gain-Bandwidth Product Requirement for an Op-Amp in a Charge-Sampling Circuit |
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211 | (2) |
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213 | (1) |
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214 | (1) |
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215 | (4) |
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216 | (3) |
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8 Discrete-Time Processing of RF Signals |
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219 | (28) |
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219 | (2) |
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8.2 Scaling of an MOS Switch |
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221 | (2) |
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223 | (3) |
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226 | (8) |
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8.5 Noise in Switched-Capacitor Filters |
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234 | (3) |
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8.6 Circuit-Design Considerations |
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237 | (5) |
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8.7 Perspective and Outlook |
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242 | (5) |
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244 | (3) |
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9 Oversampled ADC Using VCO-Based Quantizers |
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247 | (32) |
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247 | (1) |
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9.2 VCO-Quantizer Background |
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248 | (4) |
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9.3 SNDR Limitations for VCO-Based Quantization |
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252 | (5) |
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9.4 VCO Quantizer Σδ ADC Architecture |
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257 | (8) |
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9.5 Prototype Σδ ADC Example with a VCO Quantizer |
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265 | (10) |
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275 | (4) |
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276 | (3) |
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10 Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals |
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279 | (30) |
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279 | (1) |
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10.2 Mobile Terminal Challenges |
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280 | (2) |
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10.3 Research Directions Toward a Multi-Band Receiver |
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282 | (4) |
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10.4 Multi-Mode Receiver Principles and RF System Analysis for a W-CDMA Receiver |
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286 | (6) |
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10.5 W-CDMA, GSM/GPRS/EDGE Receiver Front End Without an Interstage SAW Filter |
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292 | (7) |
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10.6 Highly Integrated GPS Front End for Cellular Applications in 90-nm CMOS |
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299 | (6) |
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10.7 RX Front-End Performance Comparison |
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305 | (4) |
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305 | (4) |
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11 Digitally Enhanced Alternate Path Linearization of RF Receivers |
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309 | (38) |
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309 | (2) |
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11.2 Adaptive Feedforward Error Cancellation |
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311 | (2) |
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11.3 Architectural Concepts |
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313 | (7) |
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11.4 Alternate Feedforward Path Block Design Considerations |
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320 | (11) |
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11.5 Experimental Design of an Adaptively Linearized UMTS Receiver |
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331 | (5) |
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11.6 Experimental Results of an Adaptively Linearized UMTS Receiver |
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336 | (5) |
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341 | (6) |
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343 | (4) |
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III Transmitter Techniques |
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347 | (104) |
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12 Linearity and Efficiency Strategies for Next-Generation Wireless Communications |
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349 | (28) |
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349 | (1) |
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12.2 Power Amplifier Function |
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349 | (5) |
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12.3 Power Amplifier Efficiency Enhancement |
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354 | (8) |
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12.4 Techniques for Linearity Enhancement |
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362 | (9) |
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371 | (6) |
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372 | (5) |
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13 CMOS RF Power Amplifiers for Mobile Communications |
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377 | (34) |
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377 | (1) |
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378 | (1) |
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378 | (3) |
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13.4 Average Efficiency, Dynamic Range, and Linearity |
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381 | (5) |
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386 | (4) |
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13.6 Distortion in a Polar-Modulated Power Amplifier |
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390 | (7) |
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13.7 Design and Implementation of a Polar-Modulated Power Amplifier |
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397 | (11) |
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408 | (3) |
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408 | (3) |
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14 Digitally Assisted RF Architectures: Two Illustrative Designs |
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411 | (40) |
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411 | (1) |
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14.2 Cartesian Feedback: The Analog Problem |
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412 | (4) |
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14.3 Digital Assistance for Cartesian Feedback |
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416 | (11) |
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14.4 Multipliers, Squarers, Mixers, and VGAs: The Analog Problem |
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427 | (2) |
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14.5 Digital Assistance for Analog Multipliers |
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429 | (6) |
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435 | (16) |
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Appendix: Stability Analysis for Cartesian Feedback Systems |
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436 | (11) |
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447 | (4) |
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IV Digital Signal Processing for RF Transceivers |
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451 | (106) |
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15 RF Impairment Compensation for Future Radio Systems |
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453 | (44) |
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15.1 Introduction and Motivation |
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453 | (1) |
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15.2 Typical RF Impairments |
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454 | (15) |
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15.3 Impairment Mitigation Principles |
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469 | (11) |
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15.4 Case Studies in I/Q Imbalance Compensation |
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480 | (7) |
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487 | (10) |
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488 | (9) |
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16 Techniques for the Analysis of Digital Bang-Bang PLLs |
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497 | (36) |
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497 | (1) |
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16.2 Digital Bang-Bang PLL Architecture |
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498 | (1) |
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16.3 Analysis of the Nonlinear Dynamics of the BBPLL |
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499 | (4) |
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16.4 Analysis of the BBPLL with Markov Chains |
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503 | (5) |
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16.5 Linearization of the BBPLL |
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508 | (18) |
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16.6 Comparison of Measurements and Models |
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526 | (7) |
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531 | (2) |
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17 Low-Power Spectrum Processors for Cognitive Radios |
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533 | (24) |
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533 | (1) |
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17.2 Paradigm Shift from SDR to CR |
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534 | (1) |
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17.3 Challenge and Trends in RFIC/System |
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535 | (1) |
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17.4 Analog Signal Processing |
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536 | (1) |
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537 | (1) |
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17.6 Multi-Resolution Spectrum Sensing |
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538 | (4) |
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542 | (13) |
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555 | (2) |
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556 | (1) |
Index |
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557 | |