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Nano-CMOS and Post-CMOS Electronics: Devices and modelling, Volume 1 [Hardback]

Edited by (Louisiana State University, Division of Electrical & Computer Engineering, Baton Rouge, USA), Edited by (University of North Texas, Department of Computer Science and Engineering, USA)
  • Formāts: Hardback, 384 pages, height x width: 234x156 mm
  • Sērija : Materials, Circuits and Devices
  • Izdošanas datums: 12-Apr-2016
  • Izdevniecība: Institution of Engineering and Technology
  • ISBN-10: 1849199973
  • ISBN-13: 9781849199971
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Nano-CMOS and Post-CMOS Electronics: Devices and modelling, Volume 1Palielināt
  • Formāts: Hardback, 384 pages, height x width: 234x156 mm
  • Sērija : Materials, Circuits and Devices
  • Izdošanas datums: 12-Apr-2016
  • Izdevniecība: Institution of Engineering and Technology
  • ISBN-10: 1849199973
  • ISBN-13: 9781849199971
Citas grāmatas par šo tēmu:
Permanent link: https://www.kriso.lv/db/9781849199971.html
Keywords:
The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.



Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.



This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Preface xi
1 High-κ dielectrics and device reliability 1(34)
1.1 Introduction
1(1)
1.2 Alloying HfO2 and ZrO2
2(2)
1.3 Advanced ALD process: intermediate treatment
4(1)
1.4 SPA plasma
5(1)
1.5 Cyclic deposition and SPA plasma treatment to ALD Hf1-xZrxO2
5(8)
1.5.1 Impact of Zr addition and SPA plasma on electrical properties
8(1)
1.5.2 Reliability study by constant voltage stress
9(4)
1.6 Al incorporation into HfO2
13(14)
1.6.1 HfAlOx alloy structures
14(1)
1.6.2 Al2O3/HfO2 bilayer structures
15(1)
1.6.3 Problems with excess Al incorporation
16(1)
1.6.4 Extremely low Al incorporation in HfO2
17(10)
1.7 Conclusion
27(1)
Acknowledgment
28(1)
References
28(7)
2 High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays 35(26)
2.1 Introduction
35(3)
2.2 IMF versus pseudomorphic growth
38(1)
2.3 III-Sb on GaAs substrates
39(3)
2.4 III-Sb on silicon substrates
42(9)
2.4.1 Lattice mismatch solution: IMF layer
43(4)
2.4.2 Antiphase domains (APDs)
47(3)
2.4.3 Thermal expansion coefficient
50(1)
2.5 GaSb membranes
51(3)
2.5.1 Substrate removal technique
51(2)
2.5.2 ELO technique
53(1)
2.6 InAs and InGaSb channels on GaAs
54(3)
2.7 Conclusions
57(1)
References
57(4)
3 Anodic metal-insulator-metal (MIM) capacitors 61(38)
3.1 Introduction
61(2)
3.2 MIM capacitor
63(1)
3.3 Anodization for nanoelectronics
64(2)
3.4 Anodic alumina MIM capacitors
66(7)
3.4.1 Fabrication process flow and crystalline properties
67(1)
3.4.2 Capacitance and voltage linearity
67(3)
3.4.3 Leakage characteristics and conduction mechanisms
70(3)
3.5 Anodic titania MIM capacitors
73(6)
3.5.1 Fabrication process, oxide formation, and crystallization
74(2)
3.5.2 Capacitance, voltage linearity, and leakage characteristics
76(3)
3.6 Anodic bilayer MIM capacitors
79(5)
3.6.1 Fabrication process flow
80(1)
3.6.2 Formation of bilayer and crystallization
81(1)
3.6.3 Capacitance, voltage linearity, and leakage characteristics
82(2)
3.7 Modeling of high-k MIM capacitors
84(6)
3.7.1 Modeling the voltage linearity
85(1)
3.7.2 Macroscopic model
86(2)
3.7.3 Microscopic model
88(1)
3.7.4 Model verification
89(1)
3.8 Conclusion
90(2)
References
92(7)
4 Graphene transistors—present and beyond 99(40)
4.1 Introduction
99(1)
4.2 Fabrication of graphene
100(1)
4.3 Properties of graphene
101(13)
4.3.1 Band structure
101(2)
4.3.2 Carrier density
103(1)
4.3.3 Ambipolar field effect
104(1)
4.3.4 Conductivity
104(2)
4.3.5 Scattering mechanism
106(2)
4.3.6 High-field transport
108(1)
4.3.7 Low-field mobility
109(1)
4.3.8 Substrate and gate dielectrics
110(2)
4.3.9 Joule heating
112(1)
4.3.10 Contact resistance
112(1)
4.3.11 Quantum capacitance
113(1)
4.4 Modeling and simulation
114(5)
4.4.1 Classical transport
114(1)
4.4.2 Semiclassical transport
115(2)
4.4.3 Quantum transport
117(2)
4.5 GNR FET
119(9)
4.5.1 Graphene nanoribbon
119(4)
4.5.2 Device structure
123(1)
4.5.3 Device performance metrics
123(5)
4.6 Conclusion
128(1)
References
128(11)
5 Junction and doping-free transistors for future computing 139(30)
5.1 Introduction
139(4)
5.2 JLFET limitations
143(3)
5.3 Dopingless FET
146(2)
5.4 Junction and doping-free FET
148(18)
5.4.1 Junction and doping-free DG FET
149(10)
5.4.2 Dopingless BJT
159(7)
5.5 Conclusion
166(1)
References
166(3)
6 Nanoscale high-κ/metal-gate CMOS and FinFET based logic libraries 169(44)
6.1 Introduction
169(3)
6.2 Summary of this chapter
172(2)
6.3 HKMG bulk MOSFET
174(4)
6.3.1 HKMG device structure
175(1)
6.3.2 HKMG device modeling
176(2)
6.4 DG-FinFET device
178(5)
6.4.1 DG-FinFET device structure
178(2)
6.4.2 DG-FinFET device modeling
180(3)
6.5 The proposed methodology for logic library creation
183(4)
6.5.1 Sources of variation and nature of variability
183(1)
6.5.2 Statistical logic library characterization flow
184(3)
6.6 Power, leakage, and delay models for HKMG and DG-FinFET technology
187(4)
6.6.1 For HKMG-based technology
187(3)
6.6.2 For DG-FinFET-based technology
190(1)
6.7 Device level characterization of high-κ and FinFET
191(13)
6.7.1 For HKMG CMOS
191(8)
6.7.2 For DG-FinFET
199(5)
6.8 PVT-aware logic level characterization
204(1)
6.9 Conclusion and directions for future research
205(1)
Acknowledgment
206(1)
References
206(7)
7 FinFET and reliability considerations of next-generation processors 213(24)
7.1 Introduction
213(2)
7.2 Background
215(2)
7.2.1 NBTI degradation mechanism
215(1)
7.2.2 Target GPU architecture
216(1)
7.3 Hybrid-device warp scheduler
217(4)
7.3.1 Opportunity for improvement
217(2)
7.3.2 Two-stage scheduling
219(2)
7.4 Hybrid-device sequential-access L2 cache
221(1)
7.5 Experimental setup
222(2)
7.6 Result analysis
224(8)
7.6.1 Warp scheduler
224(4)
7.6.2 L2 cache
228(4)
7.7 Related work
232(1)
7.7.1 NBTI mitigation
232(1)
7.7.2 Characterization of FinFET reliability
233(1)
7.7.3 Hybrid-device design
233(1)
7.8 Conclusion
233(1)
References
234(3)
8 Multiple-independent-gate nanowire transistors: from technology to advanced SoC design 237(28)
8.1 Introduction
237(1)
8.2 Multiple-independent-gate field-effect transistors
238(9)
8.2.1 TIG device overview and operation
238(2)
8.2.2 Device fabrication and electrical characterization
240(3)
8.2.3 Physical understanding
243(2)
8.2.4 Performance predictions
245(2)
8.3 Circuit design opportunities
247(12)
8.3.1 Generalities
247(2)
8.3.2 Compact data path design
249(2)
8.3.3 Advanced low-power techniques
251(3)
8.3.4 Memory opportunities
254(3)
8.3.5 Case study: implementation of a Polar code decoder with MIGFETs
257(2)
8.4 Summary and conclusions
259(1)
Acknowledgment
260(1)
References
260(5)
9 Exploration of carbon nanotubes for efficient power delivery 265(22)
9.1 Introduction
265(1)
9.2 Modeling of CNTs
266(3)
9.3 CNTs for 2D power delivery network
269(5)
9.3.1 Branch analysis with CNTs
270(4)
9.4 CNTs for 3D power delivery network
274(10)
9.4.1 CNT TSV analysis
278(2)
9.4.2 Voltage drop analysis on a 3D PDN
280(4)
9.5 Conclusion
284(1)
Acknowledgment
284(1)
References
284(3)
10 Timing driven buffer insertion for carbon nanotube interconnects 287(26)
10.1 Introduction
287(3)
10.2 Problem formulation
290(1)
10.3 CNT interconnects
290(4)
10.3.1 Resistance for CNT
291(1)
10.3.2 Capacitance for CNT
292(1)
10.3.3 Inductive impact is not important
293(1)
10.3.4 Elmore delay model for bundled SWCNTs interconnects
294(1)
10.4 Timing buffering for CNT interconnects
294(5)
10.4.1 Add wire
294(2)
10.4.2 Add buffer
296(1)
10.4.3 Branch merge
296(1)
10.4.4 Add driver
297(1)
10.4.5 Pruning
298(1)
10.5 An example
299(3)
10.6 Experimental results
302(6)
10.6.1 Experimental setup
302(2)
10.6.2 Experimental results
304(4)
10.7 Conclusions
308(1)
Acknowledgment
309(1)
References
309(4)
11 Memristor modeling — static, statistical, and stochastic methodologies 313(24)
11.1 Introduction
313(2)
11.2 Static modeling
315(1)
11.2.1 TiO2 thin-film memristor
315(1)
11.2.2 Memristor static (bulk) model
316(1)
11.3 Statistical modeling
316(8)
11.3.1 Theoretical analysis
316(3)
11.3.2 3D device sample generation flow
319(3)
11.3.3 The impact of process variations
322(2)
11.4 Stochastic modeling
324(5)
11.4.1 ON and OFF static states
324(1)
11.4.2 Dynamic switching process
324(3)
11.4.3 Stochastic model verification
327(2)
11.5 Robustness of a neuromorphic system
329(3)
11.6 Conclusion
332(1)
Acknowledgment and disclaimer
332(1)
References
332(5)
12 Neuromorphic devices and circuits 337(20)
12.1 Introduction
337(1)
12.2 Emerging memory technologies
338(2)
12.3 Memristor and resistive memory
340(7)
12.3.1 Memristor
341(1)
12.3.2 Switching mechanisms
342(3)
12.3.3 Plasticity
345(1)
12.3.4 Memristor integration
346(1)
12.4 Memristive synapse circuits: current-mode design
347(4)
12.4.1 Overview
347(2)
12.4.2 Area and power consumption
349(2)
12.5 Application: image clustering
351(4)
12.5.1 Algorithm overview
351(1)
12.5.2 Hardware design
352(2)
12.5.3 Clustering MNIST images
354(1)
12.6 Summary
355(1)
Acknowledgment
355(1)
References
355(2)
Index 357
Saraju Mohanty is Professor at the Department of Computer Science and Engineering, University of North Texas, where he is the director of NanoSystem Design Laboratory (NSDL). His research interests focus on Energy-Efficient High-Performance Secure Electronic Systems. Prof. Mohanty is an inventor of 4 US patents, and an author of 200 peer-reviewed articles and 3 books. Prof. Mohanty is the current Chair of Technical Committee on Very Large Scale Integration (TCVLSI) of the IEEE Computer Society, is on the editorial board of IET Circuits, Devices and Systems, Integration and Journal of Low Power Electronics, and serves on the organizing and program committee of several international conferences.



Ashok Srivastava is Professor of Engineering at the Division of Electrical & Computer Engineering of Louisiana State University, Baton Rouge, where his research interests lie in low-power VLSI design and testability for nanoscale transistors and integration, and nanoelectronics with focus on novel emerging devices and integrated circuit design based on carbon nanotubes, graphene and other reduced dimension 2D materials. He is the author of more than 160 technical papers including conference proceedings, book chapters, a patent and a book on Carbon Based Electronics. Prof. Srivastava serves on the Editorial Review Board of Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology.