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Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing [Hardback]

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  • Formāts: Hardback, 352 pages, height x width x depth: 252x178x23 mm, weight: 848 g
  • Izdošanas datums: 04-Mar-2016
  • Izdevniecība: John Wiley & Sons Inc
  • ISBN-10: 1118869265
  • ISBN-13: 9781118869260
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Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and ComputingPalielināt
  • Formāts: Hardback, 352 pages, height x width x depth: 252x178x23 mm, weight: 848 g
  • Izdošanas datums: 04-Mar-2016
  • Izdevniecība: John Wiley & Sons Inc
  • ISBN-10: 1118869265
  • ISBN-13: 9781118869260
Citas grāmatas par šo tēmu:
Permanent link: https://www.kriso.lv/db/9781118869260.html
Keywords:

Nanomagnetic and spintronic computing devices are strong contenders for future replacements of CMOS. This is an important and rapidly evolving area with the semiconductor industry investing significantly in the study of nanomagnetic phenomena and in developing strategies to pinpoint and regulate nanomagnetic reliably with a high degree of energy efficiency. This timely book explores the recent and on-going research into nanomagnetic-based technology.

Key features:

  • Detailed background material and comprehensive descriptions of the current state-of-the-art research on each topic.
  • Focuses on direct applications to devices that have potential to replace CMOS devices for computing applications such as memory, logic and higher order information processing.
  • Discusses spin-based devices where the spin degree of freedom of charge carriers are exploited for device operation and ultimately information processing.
  • Describes magnet switching methodologies to minimize energy dissipation.
  • Comprehensive bibliographies included for each chapter enabling readers to conduct further research in this field.

Written by internationally recognized experts, this book provides an overview of a rapidly burgeoning field for electronic device engineers, field-based applied physicists, material scientists and nanotechnologists. Furthermore, its clear and concise form equips readers with the basic understanding required to comprehend the present stage of development and to be able to contribute to future development.Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing is also an indispensable resource for students and researchers interested in computer hardware, device physics and circuits design.

About the Editors and Acknowledgments xi
List of Contributors
xiii
Foreword xvii
Preface xix
1 Introduction to Spintronic and Nanomagnetic Computing Devices
1(8)
Jayasimha Atulasimha
Supriyo Bandyopadhyay
1.1 Spintronic Devices
1(2)
1.2 Nanomagnetic Devices
3(4)
1.2.1 Use of Spin Torque to Switch Nanomagnets
6(1)
1.2.2 Other Methodologies for Switching Nanomagnets
6(1)
1.3 Thinking beyond Traditional Boolean Logic
7(2)
References
7(2)
2 Potential Applications of all Electric Spin Valves Made of Asymmetrically Biased Quantum Point Contacts
9(56)
Nikhil Bhandari
Maitreya Dutta
James Charles
Junjun Wan
Marc Cahay
S.T. Herbert
2.1 Introduction
9(2)
2.2 Quantum Point Contacts
11(3)
2.3 Spin Orbit Coupling
14(4)
2.3.1 Rashba SOC (RSOC)
15(1)
2.3.2 Dresselhaus SOC (DSOC)
15(1)
2.3.3 Lateral Spin-Orbit Coupling (LSOC)
16(2)
2.4 Importance of Spin Relaxation in 1D Channels
18(2)
2.5 Observation of a 0.5 Conductance Plateau in Asymmetrically Biased QPCs in the Presence of LSOC
20(7)
2.5.1 Early Experimental Results Using InAs QPCs
20(1)
2.5.2 NEGF Conductance Calculations
20(3)
2.5.3 Spin Texture Associated with Conductance Anomalies in QPCs
23(2)
2.5.4 Prospect for Generation of Spin Polarized Current at Higher Temperature
25(1)
2.5.5 Observation of Other Anomalous Conductance Plateaus in an Asymmetrically Biased InAs/In0.52 Al0.48 as QPCs
26(1)
2.6 Intrinsic Bistability near Conductance Anomalies
27(16)
2.6.1 Experimental Results
28(2)
2.6.2 NEGF Simulations
30(13)
2.7 QPC Structures with Four In-plane SGs: Toward an All Electrical Spin Valve
43(13)
2.7.1 Preliminary Results on Four-gate QPCs
43(3)
2.7.2 Experiments
46(4)
2.7.3 Onset of Hysteresis and Negative Resistance Region
50(6)
2.8 Future Work
56(2)
2.9 Summary
58(7)
Acknowledgments
60(1)
References
60(5)
3 Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems
65(26)
Satoshi Sugahara
Yusuke Shuto
Shuu'ichirou Yamamoto
3.1 Spin-Transistor and Pseudo-Spin-Transistor
65(7)
3.1.1 Spin -- MOSFET
66(3)
3.1.2 Pseudo-Spin-MOSFET
69(3)
3.2 Energy-Efficient Logic Applications of Spin-Transistors
72(6)
3.2.1 Power Gating with Nonvolatile Retention
73(2)
3.2.2 Nonvolatile Bistable Circuits
75(1)
3.2.3 Break-even Time
76(2)
3.3 Nonvolatile SRAM Technology
78(8)
3.3.1 Static Noise Margin of Nonvolatile SRAM
79(2)
3.3.2 Energy Performance of NV-SRAM
81(5)
3.4 Application of Nonvolatile Bistable Circuits for Memory Systems
86(5)
References
88(3)
4 Spin Transfer Torque: A Multiscale Picture
91(42)
Yunkun Xie
Ivan Rungger
Kamaram Munira
Maria Stamenova
Stefano Sanvito
Avik W. Ghosh
4.1 Introduction
91(3)
4.1.1 Background
91(2)
4.1.2 STT Modeling: An Integrated Approach
93(1)
4.2 The Physics of Spin Transfer Torque
94(8)
4.2.1 Free-Electron Model for Magnetic Tunnel Junction
96(6)
4.3 First Principles Evaluation of TMR and STT
102(17)
4.3.1 The TMR Effect in the MgO Barrier
104(10)
4.3.2 Currents and Torques in NEGF
114(2)
4.3.3 First Principles Results on Spin Transfer Torque
116(3)
4.4 Magnetization Dynamics
119(6)
4.4.1 Landau-Lifshitz-Gilbert Equation
119(2)
4.4.2 Spin Torque Switching in Presence of Thermal Fluctuations
121(1)
4.4.3 Including Thermal Fluctuations: Stochastic LLG vs Fokker Planck
122(3)
4.5 Summary: Multiscaling from Atomic Structure to Error Rate
125(8)
Acknowledgments
129(1)
References
129(4)
5 Magnetic Tunnel Junction Based Integrated Logics and Computational Circuits
133(32)
Jian-Ping Wang
Mahdi Jamali
Angeline Klemm Smith
Zhengyang Zhao
5.1 Introduction
133(1)
5.2 GMR Based Field Programmable Devices
134(2)
5.3 MTJ Based Field Programmable Devices
136(9)
5.3.1 MTJ Structure and TMR Ratio
136(1)
5.3.2 MTJ Based Magneto-Logic
137(7)
5.3.3 Utilization of STT in MTJ Based Magneto-Logic
144(1)
5.4 Information Transformation between Gates
145(3)
5.4.1 Direct Communication Using Charge Current
146(2)
5.4.2 Magnetic Domain Walls for Information Transferring
148(1)
5.5 MTJ Based Logic-in-Memory Devices
148(1)
5.6 Magnetic Quantum Cellular Automata
149(6)
5.6.1 Introduction and Background
149(1)
5.6.2 Experimental Demonstrations
150(5)
5.7 All-Spin Based Magnetic Logic
155(6)
5.7.1 Nonlocal Lateral Spin Valve Background
155(1)
5.7.2 Critical Parameters for Operation
155(1)
5.7.3 Selected Review of Experimental Demonstrations
156(2)
5.7.4 Applications to All-Spin Logic Devices
158(3)
5.8 Summary
161(4)
Acknowledgment
161(1)
References
162(3)
6 Magnetization Switching and Domain Wall Motion Due to Spin Orbit Torque
165(24)
Debanjan Bhowmik
OukJae Lee
Long You
Sayeef Salahuddin
6.1 Introduction
165(1)
6.2 Theory
166(5)
6.2.1 Rashba Effect
168(1)
6.2.2 Spin Hall Effect
169(2)
6.3 Magnetic Switching Driven by Spin Orbit Torque
171(5)
6.4 Domain Wall Motion Driven by Spin Orbit Torque
176(8)
6.5 Applications of Spin Orbit Torque
184(2)
6.6 Conclusion
186(3)
References
186(3)
7 Magnonic Logic Devices
189(32)
Alexander Khitun
Alexander Kozhanov
7.1 Introduction
189(8)
7.2 Magnonic Logic Devices
197(9)
7.3 Spin Wave-Based Logic Gates and Architectures
206(6)
7.4 Discussion and Summary
212(9)
References
216(5)
8 Strain Mediated Magnetoelectric Memory
221(38)
N. Tiercelin
Y. Dusch
S. Giordano
A. Klimov
V. Preobrazhensky
P. Pernod
8.1 Introduction
221(2)
8.2 Concept of Unequivocal Strain- or Stress-Switched Nanomagnetic Memory
223(3)
8.2.1 Magnetic Configuration and Equilibrium Positions
223(2)
8.2.2 Quasi-Static Stress-Mediated Switching
225(1)
8.3 LLG Simulations -- Macrospin Model
226(5)
8.3.1 Landau-Lifshitz-Gilbert Equation and Effective Magnetic Field
226(1)
8.3.2 Memory Parameters
227(1)
8.3.3 Results of the Macrospin Model
228(3)
8.4 LLG Simulations -- Eshelby Approach
231(7)
8.4.1 Geometry of the Memory Element
232(1)
8.4.2 Coupling with the External Magnetic Field
233(1)
8.4.3 Coupling with the External Electric Field and Elastic Stress
234(1)
8.4.4 Static Behavior of the System
234(1)
8.4.5 Dynamic Behavior of the System
235(3)
8.5 Stochastic Error Analysis
238(10)
8.5.1 Statistical Mechanics of Magnetization in a Single-Domain Particle
238(5)
8.5.2 Switching Process within the Magnetoelectric Memory
243(5)
8.6 Preliminary Experimental Results
248(2)
8.6.1 Piezoelectric Actuator with in-Plane Polarization
248(1)
8.6.2 Ferroelectric Relaxors with out-of-Plane Polarization
249(1)
8.6.3 Magneto elastic Switching in a Magneto-Resistive Structure
250(1)
8.7 Conclusions
250(9)
Acknowledgments
252(1)
References
253(6)
9 Hybrid Spintronics-Strainronics
259(32)
Ayan K. Biswas
Noel D'Souza
Supriyo Bandyopadhyay
Jayasimha Atulasimha
9.1 Introduction
259(6)
9.1.1 Nanomagnetic Memory and Logic Devices: The Problem of Energy Dissipation in the Clocking Circuit
260(1)
9.1.2 Switching Nanomagnets with Strain Could Drastically Reduce Energy Dissipation: Hybrid Spintronics-Straintronics Overview
261(2)
9.1.3 Landau Lifshitz Gilbert (LLG) Equation
263(2)
9.2 Nanomagnetic Memory Switched with Strain
265(11)
9.2.1 Complete Magnetization Reversal (180° Switching): Complex out-of-Plane Dynamics
265(3)
9.2.2 Switching the Magnetization between Two Mutually Perpendicular Stable Orientations and Extension to Stable Orientations with Angular Separation >90°
268(1)
9.2.3 Complete 180° Switching with Stress Alone
269(4)
9.2.4 Mixed Mode Switching of Magnetization by 180°: Acoustically Assisted Spin Transfer Torque (STT) Switching for Nonvolatile Memory
273(3)
9.3 Straintronic Clocking of Nanomagnetic Logic
276(10)
9.3.1 Two-State Dipole Coupled Nanomagnetic Logic
276(3)
9.3.2 Four-state Multiferroic Nanomagnetic Logic (NML)
279(4)
9.3.3 Switching Error in Dipole Coupled Nanomagnetic Logic (NML)
283(1)
9.3.4 Straintronic Nanomagnetic Logic Devices (NML)
284(2)
9.4 Summary and Conclusions
286(5)
References
286(5)
10 Unconventional Nanocomputing with Physical Wave Interference Functions
291(38)
Santosh Khasanvis
Mostafizur Rahman
Prasad Shabadi
Csaba Andras Moritz
10.1 Overview
291(2)
10.2 Spin Waves Physical Layer for WIF Implementation
293(5)
10.2.1 Physical Fabric Components
295(3)
10.3 Elementary WIF Operators for Logic
298(5)
10.4 Binary WIF Logic Design
303(8)
10.4.1 Binary WIF Full Adder
303(3)
10.4.2 Parallel Counters
306(3)
10.4.3 Benchmarking Binary WIF Circuits vs. CMOS
309(1)
10.4.4 WIF Topology Exploration
310(1)
10.5 Multivalued WIF Logic Design
311(9)
10.5.1 Multivalued Operators and Implementation Using WIF
312(4)
10.5.2 Multivalued Arithmetic Circuit Example: Quaternary Full Adder
316(2)
10.5.3 Benchmarking of WIF Multivalued Circuits vs. Conventional CMOS
318(1)
10.5.4 Input/Output Logic for Data Conversion between Binary and Radix-r Domains
319(1)
10.6 Microprocessors with WIF: Opportunities and Challenges
320(6)
10.7 Summary and Future Work
326(3)
References
326(3)
Index 329
Professor Supriyo Bandyopadhyay, Virginia Commonwealth University, Virginia, USA Supriyo Bandyopadhyay is Commonwealth Professor of Electrical and Computer Engineering at Virginia Commonwealth University where he directs the Quantum Device Laboratory. Prof. Bandyopadhyay has authored and co-authored over 300 research publications and he is currently a member of the editorial board of seven international journals. He is the current Chair of the Institute of Electrical and Electronics Engineers (IEEE) Technical Committee on Spintronics (Nanotechnology Council), and past-chair of the Technical Committee on Compound Semiconductor Devices and Circuits (Electron Device Society). He has been an IEEE Electron Device Society Distinguished Lecturer and served as a Vice President of the IEEE Nanotechnology Council. Prof. Bandyopadhyay is a Fellow of the Institute of Electrical and Electronics Engineers, the Institute of Physics, American Physical Society, the Electrochemical Society and the American Association for the Advancement of Science. 

Professor Jayasimha Atulasimha, Virginia Commonwealth University, Virginia, USA Jayasimha Atulasimha is Qimonda Associate Professor of Mechanical and Nuclear Engineering with a courtesy appointment in Electrical and Computer Engineering at the Virginia Commonwealth University, where he directs the Magnetism, Magnetic Materials and Magnetic Devices (M3) laboratory. He has authored or coauthored over 60 scientific articles including more than 40 journal publications on magnetostrictive materials, magnetization dynamics, and nanomagnetic computing and has given several invited talks at conferences, workshops and universities in the USA and abroad on these topics. His research interests include nanomagnetism, spintronics, magnetostrictive materials and nanomagnet-based computing devices. He received the NSF CAREER Award for 20132018. He currently serves on the Technical Committees for Spintronics, IEEE Nanotechnology Council, ASME Adaptive Structures and Material Systems, Device Research Conference (DRC), and as a Focus Topic organizer for the APS topical group on magnetism (GMAG). He is a member of ASME, APS and an IEEE Senior Member.