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E-grāmata: Next Generation Spin Torque Memories

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This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality.

1 Emerging Memory Technologies
1(12)
1.1 Introduction
1(1)
1.2 Non-volatile Memories
2(4)
1.2.1 Phase Change Memory
3(1)
1.2.2 Resistive RAM
4(1)
1.2.3 Ferroelectric RAM
5(1)
1.2.4 Magnetoresistive RAM
5(1)
1.3 Spin Torque Based Memories
6(3)
1.3.1 Spin Transfer Torque MRAM
6(2)
1.3.2 Spin Orbit Torque MRAM
8(1)
1.3.3 Domain Wall MRAM
9(1)
1.4 Comparison of Emerging Memory Technologies
9(1)
1.5
Chapter Summary
10(3)
References
11(2)
2 Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories
13(22)
2.1 Overview of Conventional STT MRAM: Architecture and Operation
14(2)
2.2 Cell Size in Memories
16(1)
2.3 Next Generation 4F2 STT MRAM
16(4)
2.3.1 Proposed Architecture
17(1)
2.3.2 Performance Parameters and Windows
18(1)
2.3.3 Simulation Framework
19(1)
2.4 Case Study
20(8)
2.4.1 TCAD Analysis
20(1)
2.4.2 TCAD Simulation Setup
21(1)
2.4.3 Mixed-Mode Simulation Results
22(2)
2.4.4 Impact of High-k GAA Devices
24(2)
2.4.5 Impact of High-k: GD on Delay
26(2)
2.5 Proposed Fabrication Methodology
28(2)
2.6 Conclusion
30(5)
References
32(3)
3 Spin Orbit Torque MRAM
35(16)
3.1 Introduction
35(1)
3.2 SOT Device Structure
36(1)
3.3 SOT-MRAM Bit-Cell and Array Architectures
37(1)
3.4 SOT-MRAM Write and Read Mechanisms
38(5)
3.4.1 Concept of Simultaneous Read and Write Operations
41(2)
3.5 Compact Modeling of the SOT-MTJ Device
43(3)
3.5.1 Magnetization Dynamics
44(1)
3.5.2 TMR
45(1)
3.6 Design Aspects and Performance Optimization of SOT-MRAM
46(1)
3.7 Comparative Analysis of STT-MRAM and SOT-MRAM
47(4)
References
50(1)
4 Multilevel Cell MRAMs
51(20)
4.1 Introduction
51(1)
4.2 Issues with Single Level Cell (SLC) STT-/SOT-MRAM
52(1)
4.3 Multilevel Cell (MLC) Configurations
53(3)
4.3.1 STT Based MLC Configurations
53(2)
4.3.2 SOT Based MLC Configurations
55(1)
4.4 Multilevel Cell (MLC) MRAM Operations
56(4)
4.4.1 MLC STT-MRAM Write and Read Operations
56(3)
4.4.2 MLC SOT-MRAM Write and Read Operation
59(1)
4.5 Modeling and Simulation of MLC MRAMs
60(4)
4.5.1 Simulations of MLC MRAMs
61(3)
4.6 Design Aspects and Optimization of MLC MRAMs
64(3)
4.6.1 sMLC MRAMs
65(1)
4.6.2 pMLC MRAMs
66(1)
4.7 Conclusions
67(4)
References
69(2)
5 Magnetic Domain Wall Race Track Memory
71
5.1 Introduction
71(3)
5.1.1 Limitations of Existing and Emerging Memory Technologies
72(2)
5.2 Fundamentals of Domain-Wall Motion in Nanowire
74(6)
5.2.1 Magnetic Domains in Magnetic Nanowire
74(2)
5.2.2 Domain-Wall Motion in Nanowire
76(2)
5.2.3 Optimization of Domain Wall Motion
78(2)
5.3 Domain Wall MRAM
80(2)
5.3.1 DW-MRAM Write and Read Operations
80(2)
5.4 Racetrack Memory
82(4)
5.4.1 Structure of Racetrack Memory
83(1)
5.4.2 Write and Read Operations
84(2)
5.5 Racetrack Memory Based Logic Implementations
86(1)
5.6
Chapter Summary
87
References
90
Brajesh Kumar Kaushik received his Bachelor of Engineering Degree in Electronics and Communication Engineering from D.C.R. University of Science and Technology, (formerly C. R. State College of Engineering) Murthal, Haryana in 1994. He received Master of Technology Degree in Engineering Systems, from Dayalbagh Educational Institute, Agra, in 1997, and Doctorate of Philosophy (PhD) Degree in 2007 under AICTE-QIP scheme from Indian Institute of Technology Roorkee, India. He served Vinytics Peripherals Pvt. Ltd., Delhi as Research & Development Engineer in Microprocessor, Microcontroller and DSP processor based system design. He joined Department of Electronics and Communication Engineering, G.B. Pant Engineering College, Pauri Garhwal, Uttarakhand, India as Lecturer in July, 1998, where later he served as Assistant Professor from May, 2005 to May, 2006 and Associate Professor from May 2006 to Dec, 2009. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee as Assistant Professor in Dec, 2009; where since April 2014, he is working as Associate Professor. He has extensively published in several national and international journals and conferences of repute. He has also authored/co-authored several books and book chapters. He is reviewer of many international journals belonging to various publications such IEEE, IET, Elsevier, Springer, Taylor and Francis, Emerald, ETRI, PIER etc. He has also served as General Chair, Technical Chair and Keynote Speaker in many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by Government and Non-Government organizations.

He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and Microelectronics. Dr. Kaushik is Editor-in-Chief of International Journal of VLSI Design and Communication System (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; and Journal of Electrical and Electronics Engineering Research (JEEER), Academic Journals. He has received many awards and recognitions from International Biographical Center (IBC), Cambridge etc. His name has been listed in Marquis Whos Who in Science and Engineering® and Marquis Whos Who in the World®. His research interests are in the areas of High Speed Interconnects, Low power VLSI Design, Carbon Nanotube based Designs, Organic Electronics; FinFET Device Circuit Co-Design, Electronic Design Automation (EDA), Spintronics based devices and circuits.

ShivamVerma received the B.E. Degree in Electronics and Communication Engineering from Shri Vaishnav Institute of Technology and Science, Indore, India, and the M.Tech. Degree in Microelectronics from Indian Institute of Technology Varanasi, India, in 2010 and 2012, respectively. He is currently pursuing Ph.D. from Indian Institute of Technology Roorkee, India. He has published many papers in IEEE journals. His current research interests include spin transfer torque-based devices and all spin logic.



Kulkarni Anant Aravind received the B.E. Degree in Electronics Engineering from Shri Guru Gobind Singhji College of Engineering and Technology, Nanded, Maharashtra, India, in 2002, M.Tech. Degree in Electrical Engineering from Uttar Pradesh Technical University (presently Dr. A.P.J. Abdul Kalam Technical University), Lucknow, Uttar Pradesh, India in 2009, and M.Tech. Degree in Microelectronics and VLSI Design from Technocrat Institute of Technology, Bhopal, Madhya Pradesh, India in 2013. He is presently pursuing Ph.D. from Indian Institute of Technology Roorkee, India. He worked at Multitech Microsystems (Calibration Unit), Aurangabad as a trainee engineer from August, 2002 to June, 2003. He joined Department of Electronics and Communication Engineering, Marathwada Institute of Technology, Bulandshahr, India as lecturer from July, 2003 to January, 2007. He joined Electronics and Communication Engineering Department, Meerut Institute of Engineering and Technology, Meerut, India as lecturer in February, 2007 and served there till January, 2008. He joined Electrical, Electronics, and Power Engineering Department, College of Engineering, Ambajogai, Maharashtra, India, and worked as senior lecturer from February, 2007 to May, 2009 and where since June 2009, he has been working as Assistant Professor. His current research interests include Spintronics based devices, and circuits.



Sanjay Prajapati received the B.E. Degree in Electronics and Communication Engineering from Government Engineering College (GEC), Modasa, Gujarat, India in 1996 and M.Tech Degree in VLSI Design from Nirma University, Ahmedabad, Gujarat, India in 2010. He is pursuing Ph.D from the Indian Institute of Technology, Roorkee, India,since July, 2015. He served as a lecturer in the Department of Electronics and Communication Engineering, Government Polytechnic, Surat, Gujarat, India, from October, 1998 to October, 2004. He became an Assistant Professor at Vishwakarma Government Engineering College, Ahmedabad, Gujarat, India in October, 2004 and later promoted as an Associate Professor in September, 2012 at Government Engineering College, Dahod, affiliated to Gujarat Technological University, Ahmedabad, Gujarat, India. He has attended several workshops, seminars and faculty development programs of national level. He has more than seventeen years of research and academic experience. His current research interest includes Spintronic device modeling and logic design.