Preface |
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xiii | |
Glossary |
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xv | |
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1 | (12) |
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1.1 Organic Electronics: History and Market Opportunities |
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3 | (10) |
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1.1.1 Large-Area Displays |
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4 | (1) |
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5 | (1) |
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1.1.3 Radio Frequency Identification (RFID) Tag |
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6 | (1) |
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1.1.4 Technological Challenges |
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6 | (1) |
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1.1.4.1 Device Performance |
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7 | (1) |
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1.1.4.2 Device Manufacture |
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8 | (1) |
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1.1.5 Scope and Organization |
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8 | (2) |
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10 | (3) |
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2 Organic Thin Film Transistor (OTFT) Overview |
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13 | (42) |
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2.1 Organic Semiconductor Overview |
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14 | (13) |
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15 | (2) |
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17 | (1) |
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2.1.3 Microstructure and Molecular Alignment |
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18 | (3) |
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2.1.4 Material Development and Classifications |
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21 | (1) |
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22 | (2) |
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24 | (1) |
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2.1.4.3 n-Type Semiconductors |
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25 | (1) |
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2.1.5 Sensitivity to Environmental Influences |
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26 | (1) |
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2.2 OTFT Operation and Characteristics |
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27 | (7) |
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2.2.1 OTFT Parameter Extraction |
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30 | (2) |
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2.2.2 Contact Resistance Extraction |
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32 | (2) |
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2.2.3 Desirable OTFT Characteristics |
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34 | (1) |
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2.3 OTFT Device Architecture |
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34 | (4) |
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2.3.1 Top-Contact and Bottom-Contact OTFTs |
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35 | (2) |
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2.3.2 Top-Gate, Bottom-Gate, and Dual-Gate OTFTs |
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37 | (1) |
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2.4 OTFT Device Material Selection |
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38 | (11) |
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2.4.1 Organic Semiconductor |
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39 | (2) |
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41 | (2) |
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2.4.3 Electrodes/Contacts |
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43 | (2) |
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45 | (2) |
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2.4.5 Encapsulation Strategies |
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47 | (2) |
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49 | (6) |
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49 | (6) |
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3 OTFT Integration Strategies |
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55 | (46) |
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3.1 Technological Challenge in OTFT Integration |
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55 | (3) |
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3.2 Overview of Processing and Fabrication Techniques |
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58 | (18) |
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3.2.1 Deposition Methods for Organic Semiconductors |
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61 | (1) |
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3.2.1.1 Vacuum Evaporation |
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61 | (1) |
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3.2.1.2 Solution-Processed Deposition |
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61 | (1) |
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3.2.2 Patterning by Shadow Mask |
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62 | (2) |
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3.2.3 Patterning by Photolithography |
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64 | (1) |
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3.2.3.1 Photolithography Basics |
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65 | (1) |
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3.2.3.2 Photolithography Considerations for OTFTs |
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66 | (2) |
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3.2.4 Patterning by Inkjet Printing |
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68 | (3) |
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3.2.4.1 Inkjet Printing of OTFTs |
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71 | (1) |
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3.2.4.2 Improved Resolution by Surface-Energy Assisted Inkjet Printing |
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72 | (1) |
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3.2.4.3 Printing Peripheral Circuit: Vias and Interconnects |
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73 | (1) |
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3.2.5 Microcontact Printing |
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73 | (2) |
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3.2.6 Other Deposition Methods |
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75 | (1) |
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3.3 OTFT Fabrication Schemes |
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76 | (18) |
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3.3.1 Basic One-Mask Processing Scheme for Bottom-Gate OTFT |
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76 | (2) |
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3.3.2 Photolithography Scheme for Fully-Patterned and Fully-Encapsulated Bottom-Gate OTFT |
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78 | (1) |
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3.3.2.1 Directly Patterned OTFTs |
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79 | (2) |
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3.3.2.2 Indirectly Patterned OTFTs |
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81 | (2) |
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3.3.3 Hybrid Photolithography-Inkjet Printing Scheme for Fully-Patterned Bottom-Gate OTFT |
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83 | (2) |
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3.3.4 Photolithography Scheme for Top-Gate and Dual-Gate OTFTs |
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85 | (2) |
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87 | (3) |
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90 | (2) |
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92 | (1) |
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3.3.5 Fabrication Scheme Comparisons |
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93 | (1) |
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3.4 Summary and Contributions |
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94 | (7) |
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96 | (5) |
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4 Gate Dielectrics by Plasma Enhanced Chemical Vapor Deposition (PECVD) |
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101 | (46) |
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4.1 Overview of Gate Dielectrics |
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101 | (4) |
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4.1.1 Organic Dielectrics |
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101 | (3) |
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4.1.2 Inorganic Dielectrics |
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104 | (1) |
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4.2 Experimental Details and Characterization Methods |
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105 | (3) |
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4.2.1 Deposition Conditions of PECVD Silicon Nitride (SiNx) |
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105 | (1) |
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4.2.2 Thin Film Characterization Methods |
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105 | (1) |
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4.2.2.1 Fourier Transform Infrared Spectroscopy (FTIR) |
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106 | (1) |
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106 | (1) |
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4.2.2.3 X-Ray Photoelectron Spectroscopy (XPS) |
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106 | (1) |
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4.2.2.4 Atomic Force Microscopy (AFM) |
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107 | (1) |
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4.2.2.5 Contact Angle Analysis |
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107 | (1) |
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4.3 Material Characterization of PECVD SiNx Films |
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108 | (16) |
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4.3.1 Bulk/Structural Characterization |
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108 | (1) |
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4.3.1.1 FTIR Spectroscopy |
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108 | (3) |
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111 | (2) |
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113 | (1) |
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4.3.2 Surface Characterization |
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114 | (1) |
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114 | (1) |
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4.3.2.2 Surface Morphology and Roughness |
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115 | (1) |
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4.3.2.3 Chemical Composition |
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116 | (1) |
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4.3.3 Electrical Characterization |
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117 | (1) |
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117 | (3) |
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120 | (1) |
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121 | (3) |
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4.4 Electrical Characterization of OTFTs with PECVD Gate Dielectric |
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124 | (15) |
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4.4.1 300 °C SiNx Gate Dielectrics |
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125 | (4) |
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4.4.2 150° C SiNx Gate Dielectrics |
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129 | (2) |
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4.4.3 Stacked SiNx Gate Dielectrics |
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131 | (3) |
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4.4.4 200° C SiNx Gate Dielectrics |
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134 | (2) |
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4.4.5 OTFTs on Plastic Substrates |
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136 | (3) |
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4.5 Summary and Contributions |
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139 | (8) |
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142 | (5) |
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5 Dielectric Interface Engineering |
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147 | (38) |
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148 | (6) |
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5.1.1 Self Assembled Monolayer (SAM) |
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148 | (3) |
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5.1.2 Oxygen Plasma Treatment |
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151 | (1) |
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5.1.2.1 Basics of Plasma Processing (Etching) |
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152 | (2) |
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154 | (1) |
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5.3 Impact of Dielectric Surface Treatments |
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155 | (11) |
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5.3.1 Electrical Characterization |
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156 | (2) |
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5.3.2 Interface Characterization |
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158 | (1) |
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159 | (2) |
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5.3.2.2 Surface Roughness |
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161 | (2) |
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5.3.2.3 Chemical Composition |
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163 | (1) |
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164 | (2) |
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5.4 Impact of Oxygen Plasma Exposure Conditions |
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166 | (15) |
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5.4.1 Electrical Characterization |
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167 | (1) |
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5.4.1.1 Impact of Exposure Duration |
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167 | (2) |
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5.4.1.2 Impact of Exposure Power |
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169 | (1) |
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5.4.2 Interface Characterization |
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170 | (1) |
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170 | (2) |
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5.4.2.2 Surface Roughness |
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172 | (1) |
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5.4.2.3 Chemical Composition |
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173 | (4) |
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5.4.2.4 XPS Depth Profile Analysis |
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177 | (1) |
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5.4.3 Analysis and Discussion |
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178 | (3) |
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5.5 Summary and Contributions |
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181 | (4) |
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182 | (3) |
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6 Contact Interface Engineering |
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185 | (24) |
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186 | (4) |
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186 | (3) |
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6.1.2 Alkanethiol SAM on Metals |
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189 | (1) |
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190 | (2) |
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6.3 Impact of Contact Surface Treatment by Thiol SAM |
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192 | (9) |
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6.3.1 Electrical Characterization |
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192 | (5) |
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6.3.2 Interface Characterization |
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197 | (1) |
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197 | (1) |
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6.3.2.2 Surface Roughness |
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198 | (1) |
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6.3.2.3 Chemical Composition |
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198 | (1) |
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199 | (2) |
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6.4 Impact of Execution Sequence of Surface Treatment |
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201 | (4) |
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6.4.1 Electrical Characterization |
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202 | (1) |
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6.4.2 Interface Characterization |
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203 | (1) |
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203 | (1) |
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6.4.2.2 Surface Roughness |
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203 | (1) |
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6.4.2.3 Chemical Composition |
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204 | (1) |
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6.5 Summary and Contributions |
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205 | (4) |
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206 | (1) |
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207 | (2) |
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7 OTFT Circuits and Systems |
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209 | (30) |
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7.1 OTFT Requirements for Circuit Applications |
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209 | (4) |
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210 | (2) |
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212 | (1) |
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7.1.3 Current Drive Capacity |
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212 | (1) |
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213 | (1) |
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213 | (5) |
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213 | (1) |
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214 | (4) |
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7.3 Circuit Demonstration |
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218 | (14) |
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7.3.1 Fabrication Schemes |
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218 | (1) |
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219 | (4) |
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223 | (2) |
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225 | (1) |
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7.3.5 Display Pixel Circuits |
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226 | (1) |
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7.3.5.1 Conventional 2-TFT Pixel Circuit |
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226 | (3) |
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7.3.5.2 Compensating 2-TFT Pixel Circuit |
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229 | (2) |
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7.3.5.3 4-TFT Current Mirror Pixel Circuit |
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231 | (1) |
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7.4 Summary, Contributions, and Outlook |
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232 | (7) |
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7.4.1 Active-Matrix Backplane Integration |
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233 | (1) |
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7.4.2 Back-End Process Integration: Bonding and Packaging |
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234 | (1) |
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235 | (2) |
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237 | (2) |
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8 Outlook and Future Challenges |
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239 | (6) |
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240 | (1) |
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241 | (1) |
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242 | (3) |
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243 | (2) |
Index |
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245 | |