Chapter 1 Physics of Silicon Nanodevices |
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1 | (32) |
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David K. Ferry, Richard Akis, Matthew J. Gilbert, and Stephen M. Ramey |
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1 | (1) |
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2 | (6) |
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1.2.1 The Simple One-Dimensional Theory |
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3 | (1) |
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1.2.2 Ballistic Transport in the MOSFET |
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4 | (4) |
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8 | (2) |
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1.4 Quantum Behavior in the Device |
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10 | (13) |
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1.4.1 The Effective Potential |
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10 | (6) |
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1.4.1.1 Effective Carrier Wave Packet |
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11 | (2) |
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1.4.1.2 Statistical Considerations |
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13 | (3) |
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1.4.2. Quantum Simulations |
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16 | (17) |
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1.4.2.1 The Device Structure |
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16 | (1) |
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1.4.2.2 The Wave Function and Technique |
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17 | (4) |
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21 | (2) |
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1.5 Quantum Dot Single-Electron Devices |
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23 | (1) |
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1.6 Many-Body Interactions |
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23 | (3) |
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26 | (1) |
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26 | (7) |
Chapter 2 Practical CMOS Scaling |
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33 | (32) |
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33 | (1) |
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2.2 CMOS Technology Overview |
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33 | (3) |
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2.2.1 Current CMOS Device Technology |
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33 | (2) |
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2.2.2 International Technology Roadmap for Semiconductors (ITRS) Projections |
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35 | (1) |
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36 | (4) |
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37 | (1) |
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2.3.2 Characteristic Scale Length |
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38 | (2) |
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2.4 Exploratory Technology |
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40 | (8) |
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41 | (1) |
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42 | (1) |
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2.4.3 Double-Gate and Multiple-Gate FET Structures |
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43 | (5) |
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48 | (6) |
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48 | (2) |
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50 | (3) |
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2.5.3 Thermodynamic Effects |
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53 | (1) |
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2.5.4 Practical Considerations |
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53 | (1) |
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2.6 Power-Constrained Scaling Limits |
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54 | (4) |
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58 | (1) |
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58 | (1) |
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58 | (7) |
Chapter 3 The Scaling Limit of MOSFETs due to Direct Source-Drain Tunneling |
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65 | (24) |
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65 | (3) |
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68 | (7) |
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3.2.1 Concept of EJ-MOSFETs |
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68 | (2) |
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3.2.2 Fabrication of the Device Structure |
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70 | (2) |
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72 | (3) |
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3.3 Direct Source-Drain Tunneling |
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75 | (8) |
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3.3.1 Detection of the Tunneling Current |
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75 | (3) |
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3.3.2 Numerical Study of the Tunneling Current |
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78 | (5) |
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3.4 The Scaling Limit of MOSFETs |
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83 | (3) |
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3.4.1 Estimation of Direct Source-Drain Tunneling in MOSFETs |
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83 | (2) |
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3.4.2 Future Trends in Post-6-nm MOSFETs |
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85 | (1) |
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86 | (1) |
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86 | (1) |
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86 | (3) |
Chapter 4 Quantum Effects in Silicon Nanodevices |
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89 | (16) |
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89 | (1) |
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4.2 Quantum Effects in MOSFETs |
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90 | (3) |
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4.2.1 Band Structures of Silicon |
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90 | (1) |
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4.2.2 Surface Quantization |
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90 | (2) |
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4.2.3 Carrier Confinement in Thin SOI MOS Structures |
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92 | (1) |
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4.2.4 Mobility of Confined Carriers |
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92 | (1) |
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4.3 Influences of Quantum Effects in MOSFETs |
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93 | (2) |
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4.3.1 Threshold Voltage Increase in Bulk MOSFETs |
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93 | (1) |
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4.3.2 Threshold Voltage Increase in FD-SOI MOSFETs |
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94 | (1) |
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4.3.3 Mobility in Ultrathin FD-SOI MOSFETs |
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95 | (1) |
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4.4 Quantum Effects in Ultranarrow Channel MOSFETs |
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95 | (7) |
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4.4.1 Advantage of Quantum Effects in Ultranarrow Channel MOSFETs |
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95 | (1) |
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4.4.2 Threshold Voltage Increase in n-Type Narrow Channel MOSFETs |
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95 | (2) |
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4.4.3 Threshold Voltage Increase in n-Type and p-Type Narrow Channel MOSFETs |
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97 | (2) |
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4.4.4 Threshold Voltage Adjustment Using Quantum Effects |
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99 | (1) |
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4.4.5 Mobility Enhancement due to Quantum Effects |
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100 | (2) |
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102 | (1) |
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103 | (2) |
Chapter 5 Ballistic Transport in Silicon Nanostructures |
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105 | (28) |
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Hiroshi Mizuta, Katsuhiko Nishiguchi and Shunri Oda |
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105 | (1) |
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5.2 Ballistic Transport in Quantum Point Contacts |
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106 | (7) |
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5.3 Ballistic Transport in Ultra-Short Channel Vertical Silicon Transistors |
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113 | (15) |
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5.3.1 Fabrication of Nanoscale Vertical FETs |
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113 | (4) |
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5.3.2 Conductance Quantization in Nanoscale Vertical FETs |
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117 | (4) |
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5.3.3 Characteristics under a Magnetic Field |
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121 | (4) |
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5.3.4 Effects of Cross-Sectional Channel Geometries |
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125 | (3) |
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5.4 Summary and Future Subjects |
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128 | (1) |
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129 | (4) |
Chapter 6 Resonant Tunneling in Si Nanodevices |
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133 | (22) |
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Michiharu Tabe, Hiroya Ikeda, and Yasuhiko Ishikawa |
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133 | (6) |
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6.1.1 Outline of Resonant Tunneling |
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133 | (1) |
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6.1.1.1 Early Work on Resonant Tunneling |
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133 | (1) |
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6.1.1.2 Resonant Tunneling in Si-Based Materials - Si/SiGe and Si/SiO2 |
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134 | (1) |
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6.1.2 Quantum Confinement Effect in a Thin Si Layer |
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134 | (2) |
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6.1.3 Double-Barrier Structures of SiO2/Si/SiO2 Formed by Anisotropic Etching |
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136 | (3) |
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6.2 Resonant Tunneling in SiO2/Si/SiO2 |
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139 | (9) |
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6.2.1 Fabrication of an RTD |
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139 | (2) |
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6.2.2 Resonant Tunneling in the Low Voltage Region |
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141 | (2) |
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6.2.3 Hot-Electron Storage in the High-Voltage Region |
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143 | (4) |
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6.2.4 Switching of Tunnel-Modes: Comparison with a Single Barrier |
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147 | (1) |
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6.3 Zero-Dimensional Resonant Tunneling |
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148 | (4) |
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6.3.1 Coexistence of Coulomb Blockade and Resonant Tunneling |
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148 | (1) |
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6.3.2 Fabrication of a SiO2/Si-Dots/SiO2 Structure |
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149 | (2) |
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6.3.3 I-V Characteristics of an SiO2/Si-Dots/SiO2 Tunnel Diode |
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151 | (1) |
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152 | (1) |
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152 | (3) |
Chapter 7 Silicon Single-Electron Transistor and Memory |
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155 | (40) |
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155 | (3) |
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7.1.1 Quantum Dot Transistor |
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156 | (2) |
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7.2 Theoretical Background |
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158 | (7) |
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7.2.1 Energy of the Quantum Dot System |
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159 | (2) |
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7.2.2 Conductance Oscillation and Potential Fluctuation |
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161 | (1) |
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7.2.3 Transport under Finite Temperature and Finite Bias |
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162 | (3) |
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7.3 Device Structure and Fabrication |
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165 | (1) |
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7.4 Experimental Results and Analysis |
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166 | (7) |
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7.4.1 Single-Electron Quantum-Dot Transistor |
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167 | (1) |
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7.4.2 Single-Hole Quantum-Dot Transistor |
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168 | (1) |
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7.4.3 Transport Characteristics under Finite Bias |
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169 | (3) |
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7.4.4 Transport Through Excited States |
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172 | (1) |
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173 | (1) |
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7.6 Single Charge Trapping |
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174 | (2) |
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7.7 Introduction to Memory Devices |
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176 | (1) |
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177 | (2) |
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7.9 Single-Electron MOS memory (SEMM) |
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179 | (8) |
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179 | (1) |
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7.9.2 Fabrication Procedure |
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180 | (1) |
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7.9.3 Experimental Observations |
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181 | (2) |
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183 | (3) |
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7.9.5 Effects of Trap States |
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186 | (1) |
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7.10 Effect of Thicker Tunnel Oxide |
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187 | (3) |
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190 | (1) |
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191 | (4) |
Chapter 8 Silicon Memories Using Quantum and Single-Electron Effects |
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195 | (28) |
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195 | (1) |
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8.2 Single-Electron Effect |
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196 | (3) |
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8.3 Single-Electron Transistors and Their Memories |
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199 | (5) |
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8.3.2 Memories by Scaling Floating Gates of Flash Structures |
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200 | (4) |
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8.4 Modeling of Transport: Tunneling |
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204 | (4) |
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204 | (1) |
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8.4.2 Quantum Kinetic Equation |
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205 | (2) |
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8.4.3 Carrier Statistics and Charge Fluctuations |
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207 | (1) |
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8.5 Experimental Behavior of Memories |
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208 | (9) |
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8.5.1 Percolation Effects |
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212 | (1) |
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8.5.2 Limitations in Use of Field Effect |
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212 | (1) |
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8.5.3 Confinement and Random Effects in Semiconductors |
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213 | (1) |
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8.5.4 Variances due to Dimensions |
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213 | (2) |
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8.5.5 Limits due to Tunneling |
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215 | (8) |
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8.5.5.1 Tunneling in Oxide |
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215 | (1) |
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8.5.5.2 Tunneling in Silicon |
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215 | (2) |
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8.6 Can We Avoid Use of Collective Phenomena? |
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217 | (2) |
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219 | (1) |
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220 | (3) |
Chapter 9 SESO Memory Devices |
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223 | (20) |
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223 | (2) |
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9.1.1 How Nanotechnologies Solve Real Problems |
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223 | (1) |
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9.1.2 New Direction of Electronics |
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223 | (2) |
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9.2 Conventional Memory Technologies |
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225 | (2) |
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9.2.1 Classification of Conventional Memories |
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225 | (1) |
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9.2.2 Origin of DRAM Power Consumption |
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226 | (1) |
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9.3 Bandgap Enlargement in Nanosilicon |
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227 | (3) |
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230 | (2) |
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9.4.1 History: Single-Electron Devices to SESO |
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230 | (1) |
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9.4.2 Fabricated SESO Transistor |
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231 | (1) |
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232 | (4) |
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9.6 Memory-Technology Comparison |
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236 | (1) |
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9.7 SESO as On-Chip RAM Component |
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237 | (2) |
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239 | (1) |
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240 | (1) |
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240 | (3) |
Chapter 10 Few Electron Devices and Memory Circuits |
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243 | (38) |
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Kazuo Nakazato and Haroon Ahmed |
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243 | (1) |
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10.2 Current Semiconductor Memories |
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244 | (3) |
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10.2.1 Limitations of the DRAM |
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244 | (2) |
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246 | (1) |
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10.3 A New DRAM Gain Cell - The PLEDM |
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247 | (7) |
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248 | (5) |
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253 | (1) |
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10.4 Single-Electron Memory |
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254 | (22) |
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10.4.1 Single-Electron Devices |
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256 | (1) |
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10.4.2 Operation Principle of Single-Electron Memory |
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257 | (7) |
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257 | (3) |
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10.4.2.2 Global Stability |
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260 | (4) |
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10.4.3 Experimental Single-Electron Memory |
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264 | (9) |
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10.4.3.1 First Experimental Single-Electron Memory |
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264 | (5) |
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10.4.3.2 Silicon Single-Electron Memory |
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269 | (4) |
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10.4.4 Single-Electron Memory Array |
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273 | (3) |
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276 | (1) |
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277 | (4) |
Chapter 11 Single-Electron Logic Devices |
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281 | (24) |
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Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, and Hiroshi Inokawa |
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281 | (1) |
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11.2 Single-Electron Transistor (SET) |
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282 | (4) |
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11.3 Fabrication of Si SETs |
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286 | (2) |
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11.4 Logic Circuit Applications of SETs |
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288 | (13) |
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11.4.1 Fundamentals of SET Logic |
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289 | (1) |
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11.4.2 Merged SET and MOSFET Logic |
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290 | (2) |
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11.4.3 CMOS-Type Logic Circuit |
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292 | (2) |
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11.4.4 Pass-Transistor Logic |
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294 | (2) |
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296 | (2) |
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11.4.6 Multiple-Valued Operation |
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298 | (3) |
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301 | (1) |
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301 | (4) |
Index |
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305 | |