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E-grāmata: Silicon Nanowire Transistors

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  • Formāts: PDF+DRM
  • Izdošanas datums: 23-Feb-2016
  • Izdevniecība: Springer International Publishing AG
  • Valoda: eng
  • ISBN-13: 9783319271774
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Silicon Nanowire TransistorsPalielināt
  • Formāts: PDF+DRM
  • Izdošanas datums: 23-Feb-2016
  • Izdevniecība: Springer International Publishing AG
  • Valoda: eng
  • ISBN-13: 9783319271774
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This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology"s true potential for the next generation VLSI.

Dual Work Function Silicon Nanowire MOS Transistors.- Single Work Function Silicon Nanowire MOS Transistors.- Spice Modeling For Analog and Digital Applications.- High-Speed Analog Applications.- Radio Frequency (RF) Applications.- SRAM Mega Cell Design for Digital Applications.- Field-Programmable-Gate-Array (FPGA).- Integrate-And-Fire Spiking (IFS) Neuron.- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.-
1 Dual Work Function Silicon Nanowire MOS Transistors
1(26)
1.1 Device Design
1(12)
1.1.1 Introduction to Design Process
1(2)
1.1.2 The Criteria for Low Static Power Dissipation
3(1)
1.1.3 Device Structure
4(1)
1.1.4 Physical Models Used in Device Simulations
4(1)
1.1.5 Determining Metal Gate Work Function Values for NMOS and PMOS Transistors
5(1)
1.1.6 The OFF Current Requirement
6(1)
1.1.7 Intrinsic Transient Time
6(3)
1.1.8 DC Device Characteristics
9(4)
1.2 Circuit Simulations and Performance
13(10)
1.2.1 Parasitic Extraction and Post-layout Issues
13(2)
1.2.2 Transient Performance
15(2)
1.2.3 Power Dissipation
17(1)
1.2.4 Cell Layout and Gate Area Estimations
18(2)
1.2.5 Manufacturability
20(3)
1.3 Summary
23(4)
References
24(3)
2 Single Work Function Silicon Nanowire MOS Transistors
27(16)
2.1 Device Design
27(6)
2.1.1 Purpose
27(1)
2.1.2 The Criteria for Low Static Power Dissipation
28(1)
2.1.3 Device Structure
28(1)
2.1.4 Physical Models Used in Device Simulations
28(1)
2.1.5 Determining a Single Metal Gate Work Function
29(1)
2.1.6 The OFF Current Requirement for the Design
29(2)
2.1.7 Transistor Transient Characteristics: Intrinsic Transient Time
31(1)
2.1.8 DC Characteristics of the Selected NMOS and PMOS Transistors
32(1)
2.2 Circuit Performance
33(6)
2.2.1 Parasitic Extraction and Post-layout Issues
33(1)
2.2.2 Transient Performance
34(2)
2.2.3 Dynamic Power Dissipation
36(1)
2.2.4 Cell Layout Area Estimations
37(2)
2.2.5 Full Adder Comparison
39(1)
2.3 Summary
39(4)
References
40(3)
3 SPICE Modeling for Analog and Digital Applications
43(18)
3.1 BSIMSOI Device Parameters
43(16)
3.1.1 Introduction
43(1)
3.1.2 The Device
44(5)
3.1.3 Intrinsic Modeling and Parasitic Extraction
49(6)
3.1.4 Extrinsic Modeling and Parasitic Extraction
55(4)
3.2 Summary
59(2)
References
59(2)
4 High-Speed Analog Applications
61(22)
4.1 Introduction
61(1)
4.2 Brief Description of Transistor Design and Modeling
61(1)
4.3 Single-Stage CMOS SNT Amplifier
62(4)
4.3.1 The CMOS Amplifier Design
62(1)
4.3.2 The Characteristics of the CMOS Amplifier
63(3)
4.4 Differential SNT Amplifier
66(3)
4.4.1 A Single-Stage Differential Amplifier Design
66(1)
4.4.2 The Characteristics of the Differential Amplifier
67(2)
4.5 Multi-stage SNT Operational Amplifier
69(11)
4.5.1 A Two-Stage Operational Amplifier Design
69(8)
4.5.2 Characteristics of the Operational Amplifier
77(3)
4.6 Summary
80(3)
References
81(2)
5 Radio Frequency (RF) Applications
83(24)
5.1 Introduction
83(1)
5.2 Brief Description of Transistor Design and Modeling
83(1)
5.3 RF Receiver Front End
84(10)
5.3.1 Receiver Topology
84(1)
5.3.2 LC Tank Voltage-Controlled Oscillator (VCO)
84(2)
5.3.3 Mixer
86(1)
5.3.4 Low Noise Amplifier (LNA)
87(1)
5.3.5 LNA-Mixer-VCO (LMV) Cell
88(1)
5.3.6 LC Tank Oscillator as a Mixer
89(1)
5.3.7 Bias Splitting Self-Oscillating Mixer (SOM)
89(4)
5.3.8 Design of Double-Switching Self-Oscillating Degeneration LMV Cell Using SNTs
93(1)
5.4 Variable Gain Amplifier (VGA)
94(10)
5.4.1 Introduction to VGA
94(2)
5.4.2 Current-Mode Topology
96(3)
5.4.3 Voltage-Mode Topology
99(5)
5.5 Summary
104(3)
References
105(2)
6 SRAM Mega Cell Design for Digital Applications
107(14)
6.1 Introduction
107(1)
6.2 Brief Description of Transistor Design and Modeling
107(1)
6.3 SRAM Design
108(8)
6.3.1 SRAM Architecture
108(1)
6.3.2 SRAM Core
108(3)
6.3.3 Address Decoder
111(1)
6.3.4 Self-Timed Circuits
112(4)
6.4 SRAM Characteristics
116(4)
6.4.1 Parasitic Layout Extraction
116(1)
6.4.2 Read and Write Access Times
116(2)
6.4.3 Power Dissipation
118(1)
6.4.4 SRAM Layout
119(1)
6.5 Summary
120(1)
References
120(1)
7 Field-Programmable-Gate-Array (FPGA)
121(14)
7.1 Introduction
121(1)
7.2 Brief Description of Transistor Design and Modeling
121(1)
7.3 FPGA Architecture
122(7)
7.3.1 Cluster Architecture
122(1)
7.3.2 4-Input Look-Up-Table (4-LUT)
123(3)
7.3.3 An Example: A 3-bit Carry-Ripple Adder (CRA)
126(3)
7.4 FPGA Circuit Characteristics
129(4)
7.4.1 4-LUT Worst-Case Propagation Delays
129(1)
7.4.2 Intercluster Propagation Delays
129(2)
7.4.3 4-LUT Power Dissipation
131(1)
7.4.4 Flip-Flop Characteristics
132(1)
7.4.5 Cluster Layout
132(1)
7.5 Summary
133(2)
References
133(2)
8 Integrate-and-Fire Spiking (IFS) Neuron
135(10)
8.1 Introduction
135(1)
8.2 Brief Description of Transistor Design and Modeling
136(1)
8.3 IFS Neuron
136(7)
8.3.1 IFS Neuron Firing Principle
136(1)
8.3.2 IFS Neuron Design
136(5)
8.3.3 Transient Response and Power Dissipation
141(1)
8.3.4 IFS Neuron Cell Layout
142(1)
8.4 Summary
143(2)
References
144(1)
9 Direct Sequence Spread Spectrum (DSSS) Baseband Transmitter
145(16)
9.1 Introduction
145(1)
9.2 Brief Description of Transistor Design and Modeling
145(1)
9.3 DSSS Baseband Transmitter
146(5)
9.3.1 Overall Operation of the Transmitter
146(2)
9.3.2 8-PSK Modulator
148(1)
9.3.3 PN Generator
148(3)
9.3.4 Binary Mapper and Bit Multipliers
151(1)
9.4 Circuit Simulations
151(8)
9.4.1 Clock Generation Circuits
151(1)
9.4.2 Maximum Critical Paths
151(3)
9.4.3 Minimum Critical Paths
154(1)
9.4.4 Parasitic RC Extraction
154(2)
9.4.5 Power Consumption
156(2)
9.4.6 Layout
158(1)
9.5 Summary
159(2)
References
159(2)
Index 161
Ahmet Bindal received his M.S. and Ph.D. degrees in Electrical Engineering Department from the University of California, Los Angeles CA. His doctoral research was the material characterization and analysis of HEMT GaAs transistors. During his graduate studies, he was a research associate and technical consultant for Hughes Aircraft Co. In 1988, he joined the technical staff of IBM Research and Development Center in Fishkill, NY, where he worked as a device design and characterization engineer. He developed asymmetrical MOS transistors and ultra thin Silicon-On-Insulator (SOI) technologies for IBM. In 1993, he transferred to IBM in Rochester, MN, as a senior circuit design engineer to work on the floating-point unit for AS-400 main frame processor. He continued his circuit design career at Intel Corporation in Santa Clara, CA, where he designed 16-bit packed multipliers and adders for the MMX unit for Pentium II processors. In 1996, he joined Philips Semiconductors in Sunnyvale, CA, where he was involved in the designs of instruction and data caches, and various SRAM modules for the Trimedia processor. His involvement with VLSI architecture also started in Philips Semiconductors and led to the design of the Video-Out unit for the same processor. In 1998, he joined Cadence Design Systems as a VLSI architect and directed a team of engineers to design self-timed asynchronous processors. After approximately 20 years of industry work, he joined the Computer Engineering faculty at San Jose State University in 2002. His current research interests range from nano-scale electron devices to nano-scale architectures and robotics. Dr. Bindal has over 30 refereed scientific publications and 10 invention disclosures with IBM. He currently holds three U.S. patents with IBM and one with Intel Corporation.Dr. Hamedi-Hagh received his Ph.D. from the University of Toronto, Canada in 2004. He joined the Electrical Engineering Department at San Jose State University (SJSU) in 2005. His areas of research and expertise include high frequency modeling of semiconductor device structures and design of Radio Frequency, Analog and Mixed-Signal integrated circuits for wireless and wireline communication systems. Dr. Hamedi-Hagh has developed the Radio Frequency Integrated Circuits laboratory and curriculum at both graduate and undergraduate levels with over $0.5M research funding and through close collaborations with industries. He has received several California State University (CSU) professional development grants, CSU Research Funds, Research, Scholarship and Creative Activity (RSCA) grants, SJSU Planning Council Grants, College of Engineering professional development grants and Junior Faculty Career Development Grants. He is a founding member of SJSU Smart Technology and Computing Center for Complex Systems (STCCS). In 2016, he was appointed as the Mixed-Signal endowed chair of the Electrical Engineering department. Dr. Hamedi-Hagh has over 30 refereed scientific journal and conference paper publications in prestigious national and international Institutes and societies. He received the best paper award at the Micronet Symposium in Quebec, Canada in 2001 and the IEEE International Symposium on Personal, Indoor and Mobile Radio Communications in Barcelona, Spain in 2004. Dr. Hamedi-Hagh has advised several hundred projects on design of integrated circuits and systems. He holds seven US and world patents on wireless circuits, systems and cryptography. His latest patent introduces suspendance® and trajectance® laws as alternatives to Kirchhoffs laws for circuit analysis.
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