Accelerators now play a crucial role in computing systems. With the emergence of a new wave of academic and industrial high-level synthesis (HLS) tools, FPGA-based accelerators now are more accessible to software programmers. However, there are several burdens placed upon the programmers to design a high-performance accelerator when using FPGA, such as different memory and parallel programming models. Therefore, a high-level structured design approach targeting accelerator is essential. This approach advances software programming techniques to utilize FPGAs efficiently.
This book explains the concept of accelerator design using current high-level synthesis tools and techniques. It describes different types of regular and irregular accelerator patterns as a structured building block for FPGA implementation. The cutting-edge programming models based on C/C++ and OpenCL are used to explain standard computation and memory patterns through many examples and case studies. In short, this book:
- offers theory and practice of HLS parallel programming techniques for FPGA
- describes parallel patterns for regular and irregular algorithms
- contains detailed examples in C/C++ and OpenCL for HLS
- represents the efficiency of FPGA accelerators through several case studies in scientific computation and machine learning areas.
This book explains the concept of accelerator design using current high-level synthesis tools and techniques. It describes different types of regular and irregular accelerator patterns as a structured building block for FPGA implementation.
Preface; 1- Introduction; 2- FPGA-Based Embedded Systems; 3- Fundamental
of High-Level Synthesis; 4- Concurrency; 5- Concurrency Enhancement; 6-
Regular and Irregular Applications; 7- Streaming Model of Computation; 8-
Streaming Engine; 9- Map and Reduce Patterns; 10- Stencil Pattern; 11- Scan
Pattern; 12- Other Patterns; 13- K-Means Clustering 14- Deep Neural Network;
Mohammad Hosseinabady has a PhD degree in Electronics and Computer Engineering. He has been researching the subject of reconfigurable computing on field-programmable gate arrays (FPGA) for more than 20 years in several universities, including University of Tehran, Politecnico di Torino, University of Bristol, University of Southampton and Queen's University Belfast. He is currently working on high-level synthesis for FPGA. His goal is to make advanced reconfigurable technologies more accessible for everyone who may not have in-depth knowledge of FPGAs and the traditional hardware design methodologies. His research interests include high-level reliability and testability, reconfigurable architectures, dynamic resource management, and runtime power management. He has published several papers on these topics in IEE, IEEE and ACM transactions, journals and conference proceedings.
