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Vision Chips 2000 ed. [Hardback]

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Vision chips, or smart visual sensors, are those sensors that have integrated image acquisition and parallel processing, often at the pixel level, using dedicated analog and digital circuits. Vision Chips presents a systematic approach to the design and analysis of vision chips using analog VLSL. It presents algorithmic level implementation issues, from both the VLSI and computer vision points of view. It reviews the VLSI technologies and general analog VLSI design methodologies, in the context of suitability for vision chips. It describes chip-level architectural issues, including tessellation structures, pixel-processor interaction, and data read-out. It presents detailed analysis of building-blocks necessary in vision chips, including photodetectors, photocircuits, and spatial and temporal processing circuits. It addresses other important design issues, such as testing, digital noise, and mismatch. In addition Vision Chips reviews some of the past and existing implementations of smart vision sensors. It contains condensed information on more than fifty vision chips, designed by research laboratories all over the world. Novel and interesting features of each vision chip have been highlighted through informative diagrams and concise descriptions. This book is a valuable asset for researchers in the area, engineers working on the design of vision sensors, graduate students working in analog VLSI and vision, and computer vision and biological vision researchers and scientists.

Papildus informācija

Springer Book Archives
Part I Introduction and Background xvii
Introduction
1(6)
A General Overview
1(2)
Vision Chips in the Past and Present
3(2)
Analog VLSI Design Framework
4(1)
Organization of The Book
5(2)
Computer Vision for Analog VLSI
7(16)
Computational Motion Detection Algorithms
8(3)
Intensity Based Motion Detection
9(1)
Feature Based Motion Detection
10(1)
Correlation Based Motion Detection
11(1)
Biological Motion Detection Models
11(2)
Contrast Enhancement
13(10)
Computational Models for Contrast Enhancement
15(1)
Subtraction from spatial average
15(1)
Division by spatial average
16(1)
Laplacian of Gaussian (LoG)
16(1)
Even Gabor functions
17(1)
Regularization theory for surface reconstruction
18(1)
Biological Models for Contrast Enhancement
18(1)
Linear lateral inhibition
18(1)
Nonlinear lateral inhibition
19(1)
Comparison
19(4)
Analog VLSI for Computer Vision
23(22)
Analog or Digital?
24(4)
A philosophical point
24(1)
Design trade-offs
25(3)
Analog VLSI and Artificial Neural Networks
28(3)
Interconnection
28(1)
The number of neurons
29(1)
Processing elements
30(1)
Weight storage
30(1)
Feedback or learning
30(1)
Analog VLSI and Vision Chips
31(1)
Technology Base for Implementation
32(4)
CMOS
32(2)
BiCMOS
34(1)
CCD/CCD-CMOS
34(2)
GaAs
36(1)
Analog VLSI Design Methodologies
36(5)
Current Mode & Voltage Mode
37(1)
Charge Mode
38(2)
Mixed Modes
40(1)
Mixed Analog/Digital
40(1)
Mixed Continuous/Sampled
41(1)
A Mixture of All
41(1)
Summary
41(4)
Part II Synthesis of Vision Algorithms 45(84)
Vision Chips Architectures
49(16)
Pixel Level Structures and Tessellation
49(5)
Periodic Spatial Sampling and Tessellation
50(1)
Finite Detector Size
50(2)
Tessellation Structures for Vision Chips
52(1)
Spatial Re-Mapping Structures
53(1)
Sensor-Processor Architectures
54(5)
Simple Algorithms
56(1)
Spatial Processing Algorithms
57(1)
Spatio-temporal Processing Algorithms
57(2)
System Level Read-out and Communication
59(3)
Passive & Active Information Transfer
60(1)
Data Read-Out
60(2)
Summary
62(3)
Building Blocks for Vision Chips
65(36)
Photodetectors
65(3)
Photocircuits
68(7)
Logarithmic Compression Photocircuit
69(1)
Logarithmic Compression With Feedback Amplifier
70(1)
Buffered Logarithmic Photocircuit
71(1)
Adaptive Logarithmic Photocircuits
72(2)
Current Amplifier Photocircuit
74(1)
Charge-Integration Photocircuit
75(1)
Circuits and techniques for active pixel sensors
75(3)
Photocircuits in active pixel sensors
76(1)
Correlated double sampling
77(1)
Circuits for Spatial Processing
78(21)
Cellular Neural Networks
80(1)
Resistive Networks
81(1)
Stability
82(2)
Spatial Impulse Response
84(1)
Circuits and Networks for Spatial Smoothing
84(8)
Nonlinear Resistive Networks
92(2)
Resistive Networks Using Saturating Resistor
94(1)
Resistive Networks Using Resistive Fuse
94(1)
Circuits and Networks for Contrast Enhancement
94(2)
Analog Memory Elements
96(3)
Continuous Delay Elements
99(1)
Summary
99(2)
Testing vision chips
101(8)
Design for Testing
101(3)
Tests and Measurements
104(1)
Test conditions
105(1)
Steady-state tests
106(1)
Spatio-temporal tests
107(2)
Other Design Issues
109(20)
Mismatch
109(14)
Sources and Modeling of Mismatch
110(1)
Mismatch in Circuits
111(1)
Current Mirrors
112(1)
Mismatch in Interconnected Networks
113(1)
Spatial Smoothing
114(2)
Contrast Enhancement
116(7)
Interconnection
123(1)
Interconnect density
123(1)
Digital Noise
124(2)
Summary
126(3)
Part III Vision Sensors 129(76)
Spatial Vision Chips
131(32)
Mahowald and Mead's silicon retina
132(1)
Mead's adaptive retina
133(1)
Mahowald-Delbruck's Stereo Matching Chips
133(2)
Bernard et al.'s Boolean artificial retina
135(2)
Andreou and Boahen's silicon retina
137(1)
Kobayashi et al.'s image Gaussian filter
138(1)
PASIC sensor from Linkoping University
139(1)
MAPP2200 sensor from IVP
140(2)
Forchheimer-Astrom's NSIP sensor
142(1)
The foveated CCD chip
143(2)
IMEC-IBIDEM's foveated CMOS chip
145(1)
Wodnicki et al.'s foveated CMOS sensor
145(1)
Standley's Orientation Detection Chip
146(1)
Harris et al.'s Resistive Fuse Vision Chip
147(3)
DeWeerth's Localization and Centroid Computation Chip
150(1)
Ward & Syrzycki's Receptive Field Sensors
151(1)
Wu & Chiu's 2-D Silicon Retina
152(1)
Nilson et al.'s Shunting Inhibition Chip
153(2)
Keast & Sodini's CCD/CMOS Image Segmentation Chip
155(1)
Mitsubishi Electric's CMOS Artificial Retina with VSP
156(2)
Venier et al.'s Solar Illumination Monitoring Chip
158(1)
Mitsubishi Electric's Optical Neurochip and Retina
159(1)
Yu et al.'s Optical Neurochip
160(3)
Spatio-Temporal Vision Chips
163(36)
Lyon's eye
164(1)
Tanner and Mead's correlating motion detection chip
164(1)
Tanner and Mead's optic flow motion detection chip
165(2)
Bair and Koch's motion detection chip
167(1)
Delbruck's focusing chip
168(1)
Delbruck's velocity tuned motion sensor
169(1)
Meitzler et al.'s sampled-data motion chip
170(1)
Moini et al.'s insect vision-based motion detection chip
171(2)
Moini et al.'s second insect vision-based motion detection chip
173(2)
Dron's multi-scale veto CCD motion sensor
175(1)
Horiuchi et al.'s delay line-based motion detection chip
176(1)
Gottardi and Yang's CCD/CMOS motion sensor
177(2)
Kramer et al.'s velocity sensor
179(1)
Indiveri et al.'s time-to-crash sensor
179(3)
Indiveri et al.'s direction-of-heading detector
182(2)
McQuirk's CCD focus of expansion estimation chip
184(1)
Sarpeshkar et al.'s pulse mode motion detector
185(1)
Meitzler et al.'s 2-D position and motion detection chip
186(2)
Aizawa et al.'s Image Sensor with Compression
188(1)
Hamamoto et al.'s Image Sensor With Motion Adaptive Storage Time
189(1)
Espejo et al.'s Smart Pixel CNN
190(3)
Moini et al.'s Shunting Inhibition Vision Chip
193(1)
Etienne-Cummings et al.'s Motion Detector Chip
194(1)
CSEM's Motion Detector Chip for Pointing Devices
195(4)
Analog VLSI Chips for Vision Processing
199(6)
Hakkaranien-Lee's AVD CCD Chip for Stereo Vision
199(2)
Erten's CMOS Chip for Stereo Correspondence
201(4)
Part IV Case Studies 205(38)
Bugeye II: The Second Insect Vision Motion Detection Chip
209(14)
Testability and Reconfigurability
210(2)
Testability
210(1)
Reconfigurability
211(1)
Photodetector
212(1)
Multiplicative Noise Cancellation
212(4)
The source of multiplicative noise
212(2)
Reducing multiplicative noise
214(2)
TCD circuit
216(6)
Summary
222(1)
Bugeye V
223(8)
Architecture
223(2)
Photocircuits in Bugeye V
225(3)
Motion Detection
228(1)
Summary
229(2)
MNCSI
231(12)
Shunting Inhibition
231(3)
Current Mode Implementation of SI
232(1)
Simulation and Test Results of the SI Circuit
233(1)
MNC Circuit
234(6)
Using the Substrate Node
236(3)
Light-Modulated MOS Transistors
239(1)
Summary
240(3)
Part V Appendices 243(30)
A Quantum Efficiency of Photodetectors
245(20)
A.1 Quantum Efficiency of a Vertical Junction Diode
246(3)
A.2 Quantum Efficiency of a Lateral Junction Diode
249(3)
A.3 Quantum Efficiency of a Vertical Bipolar transistor
252(4)
A.4 Quantum Efficiency of a Lateral Bipolar Photodetector
256(5)
A.5 Mixed structures
261(1)
A.6 Quantum Efficiency of a Photogate
261(4)
B Analysis of Second-Order Resistive Networks
265(8)
B.1 Stability
265(4)
B.2 Impulse Response
269(4)
Bibliography 273(23)
Index 296