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Chemical-Mechanical Polishing of Low Dielectric Constant Polymers and Organosilicate Glasses: Fundamental Mechanisms and Application to IC Interconnect Technology Softcover reprint of the original 1st ed. 2002 [Mīkstie vāki]

  • Formāts: Paperback / softback, 229 pages, height x width: 235x155 mm, weight: 385 g, XIV, 229 p., 1 Paperback / softback
  • Izdošanas datums: 23-Feb-2014
  • Izdevniecība: Springer-Verlag New York Inc.
  • ISBN-10: 1461354242
  • ISBN-13: 9781461354246
  • Mīkstie vāki
  • Cena: 136,16 €*
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  • Standarta cena: 160,19 €
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  • Formāts: Paperback / softback, 229 pages, height x width: 235x155 mm, weight: 385 g, XIV, 229 p., 1 Paperback / softback
  • Izdošanas datums: 23-Feb-2014
  • Izdevniecība: Springer-Verlag New York Inc.
  • ISBN-10: 1461354242
  • ISBN-13: 9781461354246
As semiconductor manufacturers implement copper conductors in advanced interconnect schemes, research and development efforts shift toward the selection of an insulator that can take maximum advantage of the lower power and faster signal propagation allowed by copper interconnects. One of the main challenges to integrating a low-dielectric constant (low-kappa) insulator as a replacement for silicon dioxide is the behavior of such materials during the chemical-mechanical planarization (CMP) process used in Damascene patterning. Low-kappa dielectrics tend to be softer and less chemically reactive than silicon dioxide, providing significant challenges to successful removal and planarization of such materials.



The focus of this book is to merge the complex CMP models and mechanisms that have evolved in the past decade with recent experimental results with copper and low-kappa CMP to develop a comprehensive mechanism for low- and high-removal-rate processes. The result is a more in-depth look into the fundamental reaction kinetics that alter, selectively consume, and ultimately planarize a multi-material structure during Damascene patterning.

Papildus informācija

Springer Book Archives
1: Overview of IC Interconnects.- 1.1 Silicon Ic Beol Technology
Trends.- 1.2 Sia Roadmap Interconnect Projections.- 1.3 Low-? Requirements
and Materials.- 1.4 Need for Low-? CMP Process Understanding.- 1.5 Summary.-
1.6 References.- 2: Low-? Interlevel Dielectrics.- 2.1 Fluorinated Glasses.-
2.2 Silsesquioxanes.- 2.3 Organosilicate Glasses.- 2.4 Polymers.- 2.5
Fluorinated Hydrocarbons.- 2.6 Nanoporous Silica Films.- 2.7 Other Porous
Materials.- 2.8 References.- 3: Chemical-Mechanical Planarization (CMP).- 3.1
CMP Process Description.- 3.2 CMP Processes With Copper Metallization.- 3.3
CMP of Low-? Materials.- 3.4 CMP Process Models.- 3.5 Langmuir-Hinshelwood
Surface Kinetics in CMP Modeling.- 3.6 References.- 4: CMP of BCB and SiLK
Polymers.- 4.1 Removal Rate in Copper Slurries.- 4.2 Surface Roughness.- 4.3
Surface and Bulk Film Chemistry.- 4.4 Effect of Cure Conditions on BCB and
Silk Removal.- 4.5 Effect of CMP and BCB and Silk Film Hardness.- 4.6
Comparison of BCB and Silk CMP with other Polymer CMP.- 4.7 Summary.- 4.8
References.- 5: CMP of Organosilicate Glasses.- 5.1 Effect of Film Carbon
Content.- 5.2 Surface Roughness.- 5.3 Surface and Bulk Film Chemistry.- 5.4
Copper Damascene Patterning with OSG Dielectrics.- 5.5 Summary.- 5.6
References.- 6: Low-? CMP Model Based on Surface Kinetics.- 6.1 Isolation of
the Chemical Effects in Silk CMP.- 6.2 CMP with Simplified Model Silk
Slurries.- 6.3 Phenomenological Model for CMP Removal.- 6.4 Five Step Removal
Model Using Modified Langmuir-Hinshelwood Kinetics for Silk CMP.- 6.5 Two
Step Removal Model Using Heterogeneous Catalysis for Silk CMP.- 6.6
Extendibility of Model to Describe the CMP of Other Materials.- 6.7
References.- 7: Copper CMP Model Based Upon Fluid Mechanics and Surface
Kinetics.- 7.1 FlowModel.- 7.2 Copper Removal Model.- 7.3 Model Results.- 7.4
Copper CMP Experiments with Potassium Dichromate Based Slurry.- 7.5 Summary.-
7.6 References.- 8: Future Directions in IC Interconnects and Related Low-?
ILD Planarization Issues.- 8.1 Planarization of Interconnects with Ultra
Low-? ILDS.- 8.2 Alternatives for the Post-Copper/Ultra Low-? Interconnect
Era.- 8.3 3D Wafer-Scale Integration Using Dielectric Bonding Glues and
Inter-Wafer Interconnection with Copper Damascene Patterning.- 8.4 Summary
and Conclusions.- 8.5 References.- Appendices.- Appendix A: Experimental
Procedures and Techniques.- Appendix B: XPS Depth-Profile Data.- Appendix C:
CMP Data for Anomalous Silk Removal Behavior.